 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Features * Incorporates the ARM7TDMI(R) ARM(R) Thumb(R) Processor - High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE In-circuit Emulation, Debug Communication Channel Support 64 Kbytes of Internal High-speed Flash, Organized in 512 Pages of 128 Bytes - Single Cycle Access at Up to 30 MHz in Worst Case Conditions, Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed - Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms - 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit - Fast Flash Programming Interface for High Volume Production 16 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) - Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) - Based on Power-on Reset and Low-power Factory-calibrated Brownout Detector - Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) - Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) - Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode - Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) - 12-bit key-protected Programmable Counter - Provides Reset or Interrupt Signals to the System - Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) - 32-bit Free-running Counter with Alarm - Runs Off the Internal RC Oscillator One Parallel Input/Output Controller (PIOA) - Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Eleven Peripheral Data Controller (PDC) Channels One USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 328-byte Configurable Integrated FIFOs One Synchronous Serial Controller (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support - Full Modem Line Support on USART1 One Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects * * * * * * AT91 ARM(R) Thumb(R)-based Microcontrollers AT91SAM7S64 Preliminary * * * * * * * * * * * 6070A-ATARM-28-Oct-04 * One Three-channel 16-bit Timer/Counter (TC) * * * * * * - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) - Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os IEEE 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies - Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components - 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply - 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: Up to 55 MHz at 1.65V and 85xC Worst Case Conditions Available in a 64-lead LQFP Package * * Description Atmel's AT91SAM7S64 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 64 Kbyte high-speed Flash and a 16 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality. The AT91SAM7S64 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The AT91SAM7S64 is a general-purpose microcontroller. Its integrated USB Device port makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular phone. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market. 2 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Block Diagram Figure 1. AT91SAM7S64 Block Diagram TDI TDO TMS TCK JTAGSEL JTAG SCAN ICE ARM7TDMI Processor 1.8 V Voltage Regulator VDDIN GND VDDOUT VDDCORE TST FIQ System Controller AIC PIO IRQ0-IRQ1 Memory Controller Embedded Flash Controller Address Decoder Misalignment Detection VDDIO SRAM 16 Kbytes PCK0-PCK2 PLLRC XIN XOUT PLL OSC RCOSC PMC Abort Status VDDFLASH Flash 64 Kbytes ERASE VDDCORE BOD POR Reset Controller Peripheral Bridge PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1 VDDCORE NRST Peripheral Data Controller 11 Channels PIT WDT RTT DRXD DTXD PIO Fast Flash Programming Interface APB PDC FIFO Transceiver DBGU PDC USB Device DDM DDP PIOA RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 RI1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF PDC PWMC PDC USART0 PDC PDC SSC PDC USART1 Timer Counter PIO PDC PDC TC0 TC1 SPI PDC PDC TC2 TWI PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK ADC PIO 3 6070A-ATARM-28-Oct-04 Signal Description Table 1. Signal Description List Signal Name Function Power VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL GND Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply I/O Lines Power Supply Core Power Supply PLL Ground Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK2 Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Input Output Input Output ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input Input Output I/O Input Low Pull-Up resistor Pull-down resistor Input High Pull-down resistor Input Input Output Input Input No pull-up resistor Pull-down resistor No pull-up resistor No pull-up resistor 3.0V to 3.6V 1.85V nominal 3.0V to 3.6V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Type Active Level Comments 4 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 1. Signal Description List (Continued) Signal Name Function PIO PA0 - PA31 Parallel IO Controller A I/O USB Device Port DDM DDP USB Device Port Data USB Device Port Data + USART SCK0 - SCK1 TXD0 - TXD1 RXD0 - RXD1 RTS0 - RTS1 CTS0 - CTS1 DCD1 DTR1 DSR1 RI1 Serial Clock Transmit Data Receive Data Request To Send Clear To Send Data Carrier Detect Data Terminal Ready Data Set Ready Ring Indicator I/O I/O Input Output Input Input Output Input Input Synchronous Serial Controller TD RD TK RK TF RF Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Timer/Counter TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2 External Clock Inputs I/O Line A I/O Line B PWM Controller PWM0 - PWM3 PWM Channels SPI MISO MOSI SPCK NPCS0 NPCS1-NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 to 3 I/O I/O I/O I/O Output Low Low Output Input I/O I/O Output Input I/O I/O I/O I/O Analog Analog Pulled-up input at reset Type Active Level Comments 5 6070A-ATARM-28-Oct-04 Table 1. Signal Description List (Continued) Signal Name Function Type Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O Analog-to-Digital Converter AD0-AD3 AD4-AD7 ADTRG ADVREF Analog Inputs Analog Inputs ADC Trigger ADC Reference Analog Analog Input Analog Fast Flash Programming Interface PGMEN0-PGMEN1 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input Low High Low Low Digital pulled-up inputs at reset Analog Inputs Active Level Comments 6 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Package and Pinout The AT91SAM7S64 is available in a 64-lead LQFP package. 64-lead LQFP Mechanical Figure 2 shows the orientation of the 64-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Overview Figure 2. 64-lead LQFP Package Pinout (Top View) 48 49 33 32 64 1 16 17 Pinout Table 2. AT91SAM7S64 Pinout in 64-lead LQF Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADVREF GND AD4 AD5 AD6 AD7 VDDIN VDDOUT PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA21/PGMD9 VDDCORE PA19/PGMD7/AD2 PA22/PGMD10 PA23/PGMD11 PA20/PGMD8/AD3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDDIO PA16/PGMD4 PA15/PGM3 PA14/PGMD2 PA13/PGMD1 PA24/PGMD12 VDDCORE PA25/PGMD13 PA26/PGMD14 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TDI PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA27/PGMD15 PA28 NRST TST PA29 PA30 PA3 PA2 VDDIO GND PA1/PGMEN1 PA0/PGMEN0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TDO JTAGSEL TMS PA31 TCK VDDCORE ERASE DDM DDP VDDIO VDDFLASH GND XOUT XIN/PGMCK PLLRC VDDPLL 7 6070A-ATARM-28-Oct-04 Power Considerations Power Supplies The AT91SAM7S64 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: * * * * * VDDIN pin. It powers the voltage regulator; voltage ranges from 3.0V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND. VDDOUT pin. It is the output of the 1.8V voltage regulator. VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V, 3.3V nominal. VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. * No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. Power Consumption The AT91SAM7S64 has a static current of less than 60 A on VDDCORE at 25C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 A static current. The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA. Voltage Regulator The AT91SAM7S64 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 A static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 A static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 F (or 3.3 F) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 F X7R. 8 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Typical Powering Schematics 3.3V Single Supply The AT91SAM7S64 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems. Figure 3. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN 3.3V VDDOUT Voltage Regulator VDDCORE VDDPLL 9 6070A-ATARM-28-Oct-04 I/O Lines Considerations JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. Test Pin The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S64 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be both tied high. Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results. Reset Pin The pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system. The pin NRST integrates a permanent pull-up resistor to VDDIO. ERASE Pin The pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. All the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset. PIO Controller A Lines I/O Line Drive Levels The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 150 mA. 10 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Processor and Architecture ARM7TDMI Processor * * RISC processor based on ARMv4T Von Neumann architecture - - - * - - - Runs at up to 55 MHz, providing 0.9 MIPS/MHz ARM (R) high-performance 32-bit instruction set Thumb(R) high code density 16-bit instruction set Instruction Fetch (F) Instruction Decode (D) Execute (E) Two instruction sets Three-stage pipeline architecture Debug and Test Features * Integrated embedded in-circuit emulator - - - Two watchpoint units Test access port accessible through a JTAG protocol Debug communication channel Two-pin UART Debug communication channel interrupt handling Chip ID Register * Debug Unit - - - * IEEE1149.1 JTAG Boundary-scan on all digital pins Bus Arbiter - Handles requests from the ARM7TDMI and the Peripheral Data Controller Three internal 1 Mbyte memory areas One 256 Mbyte embedded peripheral area Source, Type and all parameters of the access leading to an abort are saved Facilitates debug by detection of bad pointers Alignment checking of all data accesses Abort generation in case of misalignment Remaps the SRAM in place of the embedded non-volatile memory Allows handling of dynamic exception vectors Embedded Flash interface, up to three programmable wait states Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states Key-protected program, erase and lock/unlock sequencer Single command for erasing, programming and locking operations Interrupt generation in case of forbidden operation Address decoder provides selection signals for - - Memory Controller * * * Abort Status Registers - - * Misalignment Detector - - * Remap Command - - * Embedded Flash Controller - - - - - 11 6070A-ATARM-28-Oct-04 Peripheral Data Controller * * Handles data transfer between peripherals and memories Eleven channels - - - - - Two for each USART Two for the Debug Unit Two for the Serial Synchronous Controller Two for the Serial Peripheral Interface One for the Analog-to-digital Converter One Master Clock cycle needed for a transfer from memory to peripheral Two Master Clock cycles needed for a transfer from peripheral to memory * Low bus arbitration overhead - - * Next Pointer management for reducing interrupt latency requirements 12 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Memory * 64 Kbytes of Flash Memory - - - - - - - - * - 512 pages of 128 bytes Fast access time, 30 MHz single-cycle access in Worst Case conditions Page programming time: 4 ms, including page auto-erase Page programming without auto-erase: 2 ms Full chip erase time: 10 ms 10,000 write cycles, 10-year data retention capability 16 lock bits, each protecting 16 sectors of 32 pages Protection Mode to secure contents of the Flash Single-cycle access at full speed 16 Kbytes of Fast SRAM Memory Mapping Internal SRAM The AT91SAM7S64 embeds a high-speed 16-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7S64 features one bank of 64 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 4. Internal Memory Mapping 0x0000 0000 0x000F FFFF Internal Flash Flash Before Remap SRAM After Remap Internal Flash 1 M Bytes 0x0010 0000 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Internal SRAM 1 M Bytes Undefined Areas (Abort) 253 M Bytes 0x0FFF FFFF 13 6070A-ATARM-28-Oct-04 Embedded Flash Flash Overview The Flash of the AT91SAM7S64 is organized in 512 pages of 128 bytes. The 65,536 bytes are organized in 32-bit words. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: * * * * * programming of the access parameters of the Flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. Lock Regions The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S64 contains 16 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes. If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. Security Bit Feature The AT91SAM7S64 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 50 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 14 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Non-volatile Brownout Detector Control Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain as defined by the user. These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. * GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. * Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high. Fast Flash Programming Interface 15 6070A-ATARM-28-Oct-04 System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 5. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller irq0-irq1 fiq periph_irq[2..14] nirq Advanced Interrupt Controller int nfiq proc_nreset PCK debug ARM7TDMI pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq ice_nreset force_ntrst MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en gpnvm[1] flash_wrdis ice_nreset jtag_nreset Debug Unit dbgu_irq force_ntrst dbgu_txd security_bit Periodic Interval Timer Real-Time Timer Watchdog Timer wdt_fault WDRPROC bod_rst_en pit_irq flash_poe rtt_irq flash_wrdis cal wdt_irq gpnvm[0..1] Embedded Flash MCK proc_nreset BOD Reset Controller periph_nreset proc_nreset Memory Controller POR flash_poe rstc_irq SLCK NRST Voltage Regulator Mode Controller standby Voltage Regulator cal RCOSC XIN SLCK periph_clk[2..14] pck[0-2] UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend OSC XOUT MAINCK Power Management Controller PCK UDPCK MCK USB Device Port PLLRC PLL PLLCK pmc_irq int idle periph_clk[4..14] periph_nreset periph_nreset usb_suspend periph_nreset periph_clk[2] dbgu_rxd periph_irq{2] irq0-irq1 Embedded Peripherals periph_irq[4..14] PIO Controller fiq dbgu_txd in PA0-PA31 out enable 16 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 6 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space. Figure 6. System Controller Mapping Address 0xFFFF F000 Peripheral Peripheral Name Size AIC 0xFFFF F1FF 0xFFFF F200 Advanced Interrupt Controller 512 Bytes/128 registers DBGU 0xFFFF F3FF 0xFFFF F400 Debug Unit 512 Bytes/128 registers PIOA 0xFFFF F5FF 0xFFFF F600 PIO Controller A 512 Bytes/128 registers Reserved 0xFFFF FBFF 0xFFFF FC00 PMC 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller 256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 4 Bytes/1 register RSTC Reserved RTT PIT WDT Reserved VREG Reserved MC 0xFFFF FFFF Memory Controller 256 Bytes/64 registers 17 6070A-ATARM-28-Oct-04 Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The AT91SAM7S64 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE. Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1s. The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of 2% and is factory calibrated. The brownout detector is low-power, as it consumes less than 20 A static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1A. The deactivation is configured through the GPNVM bit 0 of the Flash. Brownout Detector and Power-on Reset 18 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: * * * * RC Oscillator range is between 22 KHz and 42 KHz Main Oscillator frequency ranges between 3 and 20 MHz Main Oscillator can be bypassed PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 7. Clock Generator Block Diagram Clock Generator Embedded RC Oscillator Slow Clock SLCK XIN XOUT Main Oscillator Main Clock MAINCK PLLRC PLL and Divider PLL Clock PLLCK Status Control Power Management Controller 19 6070A-ATARM-28-Oct-04 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: * * * * * the Processor Clock PCK the Master Clock MCK the USB Clock UDPCK all the peripheral clocks, independently controllable three programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 8. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int periph_clk[2..14] Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 pck[0..2] USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4 usb_suspend UDPCK Advanced Interrupt Controller * * Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor Individually maskable and vectored interrupt sources - - - - - Source 0 is reserved for the Fast Interrupt Input (FIQ) Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control the peripheral interrupts or external interrupts Programmable edge-triggered or level-sensitive internal sources Programmable positive/negative edge-triggered or high/low level-sensitive external sources Drives the normal interrupt of the processor Handles priority of the interrupt sources Higher priority interrupts can be served during service of lower priority interrupt * 8-level Priority Controller - - - 20 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * Vectoring - - - * * * - - - Optimizes interrupt service routine branch and execution One 32-bit vector register per interrupt source Interrupt vector register reads the corresponding current interrupt vector Easy debugging by preventing automatic operations Permits redirecting any interrupt source on the fast interrupt Provides processor synchronization on events without triggering an interrupt Protect Mode Fast Forcing General Interrupt Mask Debug Unit * Comprises: - - - - One two-pin UART One Interface for the Debug Communication Channel (DCC) support One set of Chip ID Registers One interface providing ICE Access Prevention Implemented features are compatible with the USART Programmable Baud Rate Generator Parity, Framing and Overrun Error Automatic Echo, Local Loopback and Remote Loopback Channel Modes Offers visibility of COMMRX and COMMTX signals from the ARM Processor Identification of the device revision, sizes of the embedded memories, set of peripherals Chip ID is 0x27090540 (VERSION 0) * Two-pin UART - - - - * * Debug Communication Channel Support - - - Chip ID Registers Periodic Interval Timer Watchdog Timer * * * * 20-bit programmable counter plus 12-bit interval counter 12-bit key-protected Programmable Counter running on prescaled SLCK Provides reset or interrupt signals to the system Counter may be stopped while the processor is in debug state or in idle mode 32-bit free-running counter with alarm running on prescaled SLCK Programmable 16-bit prescaler for SLCK accuracy compensation One PIO Controller, controlling 32 I/O lines Fully programmable through set/clear registers Multiplexing of two peripheral functions per I/O line For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) - - - Input change interrupt Half a clock period glitch filter Multi-drive option enables driving in open drain Real-time Timer * * PIO Controller * * * * 21 6070A-ATARM-28-Oct-04 - - * Programmable pull-up on each I/O line Pin data status register, supplies visibility of the level on the pin at any time Synchronous output, provides Set and Clear of several I/O lines in a single write Voltage Regulator Controller The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 22 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Peripherals Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 9. User Peripheral Mapping Peripheral Name 0xF000 0000 Size Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 TC0, TC1, TC2 Timer/Counter 0, 1 and 2 16 Kbytes Reserved 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000 UDP USB Device Port 16 Kbytes Reserved 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 TWI Two-Wire Interface 16 Kbytes Reserved 0xFFFC 0000 0xFFFB FFFF USART0 0xFFFC 3FFF Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 16 Kbytes 0xFFFC 4000 0xFFFC 7FFF 0xFFFC 8000 USART1 16 Kbytes Reserved 0xFFFC BFFF 0xFFFC C000 PWMC 0xFFFC FFFF 0xFFFD 0000 PWM Controller 16 Kbytes Reserved 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF SSC Serial Synchronous Controller 16 Kbytes 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 ADC Analog-to-Digital Converter 16 Kbytes Reserved 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 SPI Serial Peripheral Interface 16 Kbytes Reserved 0xFFFE FFFF 23 6070A-ATARM-28-Oct-04 Peripheral Multiplexing on PIO Lines The AT91SAM7S64 features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 3 on page 25 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on the PIO Controller A. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated in the table. All pins reset in their Parallel I/O lines function are configured in input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected. 24 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Controller A Multiplexing Table 3. Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A PWM0 PWM1 PWM2 TWD TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK TF TK TD RD RK RF RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DTR1 DSR1 RI1 IRQ1 NPCS1 Peripheral B TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 FIQ IRQ0 PCK1 NPCS3 PWM0 PWM1 PWM2 TIOA2 TIOB2 TCLK1 TCLK2 NPCS2 PCK2 AD0 AD1 AD2 AD3 Comments High-Drive High-Drive High-Drive High-Drive Function Application Usage Comments 25 6070A-ATARM-28-Oct-04 Peripheral Identifiers The AT91SAM7S64 embeds a wide range of peripherals. Table 4 defines the Peripheral Identifiers of the AT91SAM7S64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 4. Peripheral Identifiers Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 29 30 31 Peripheral Mnemonic AIC SYSIRQ PIOA Reserved ADC(1) SPI US0 US1 SSC TWI PWMC UDP TC0 TC1 TC2 Reserved AIC AIC Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 Analog-to Digital Converter Serial Peripheral Interface USART 0 USART 1 Synchronous Serial Controller Two-wire Interface PWM Controller USB Device Port Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 (1) Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I/O Controller A External Interrupt FIQ Note: 1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. Serial Peripheral Interface * Supports communication with external serial devices - - - - Four chip selects with external decoder allow communication with up to 15 peripherals Serial memories, such as DataFlash(R) and 3-wire EEPROMs Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors External co-processors 8- to 16-bit programmable data length per chip select Programmable phase and polarity per chip select Programmable transfer delays between consecutive transfers and between clock and data per chip select Programmable delay between consecutive transfers * Master or slave serial peripheral bus interface - - - - 26 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary - - Selectable mode fault detection Maximum frequency at up to Master Clock Two-wire Interface * * * * Master Mode only Compatibility with standard two-wire serial memories One, two or three bytes for slave address Sequential read/write operations Programmable Baud Rate Generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications - - - - - - - - - - - 1, 1.5 or 2 stop bits in Asynchronous Mode 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection, overrun error detection MSB or LSB first Optional break generation and detection By 8 or by 16 over-sampling receiver frequency Hardware handshaking RTS - CTS Modem Signals Management DTR-DSR-DCD-RI on USART1 Receiver time-out and transmitter timeguard Multi-drop Mode with address generation and detection USART * * * * * * RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - - - NACK handling, error counter with repetition and iteration limit Communication at up to 115.2 Kbps Remote Loopback, Local Loopback, Automatic Echo IrDA modulation and demodulation Test Modes Serial Synchronous Controller * * * * * Provides serial synchronous communication links used in audio and telecom applications Contains an independent receiver and transmitter and a common clock divider Offers a configurable frame sync and data length Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal Three 16-bit Timer Counter Channels - Three output compare or two input capture Frequency measurement Event counting Interval measurement Wide range of functions including: - - - Timer Counter * * 27 6070A-ATARM-28-Oct-04 - - - - * - - Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Three external clock inputs Five internal clock inputs, as defined in Table 5 Each channel is user-configurable and contains: Table 5. Timer Counter Clocks Assignment TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 - - Two multi-purpose input/output signals Two global registers that act on all three TC channels PWM Controller * * Four channels, one 16-bit counter per channel Common clock generator, providing thirteen different clocks - - One Modulo n counter providing eleven clocks Two independent linear dividers working on modulo n counter outputs Independent enable/disable commands Independent clock selection Independent period and duty cycle, with double bufferization Programmable selection of the output waveform polarity Programmable center or left aligned output waveform * Independent channel programming - - - - - USB Device Port * * * * USB V2.0 full-speed compliant,12 Mbits per second. Embedded USB V2.0 full-speed transceiver Embedded 328-byte dual-port RAM for endpoints Four endpoints - - - - Endpoint 0: 8 bytes Endpoint 1 and 2: 64 bytes ping-pong Endpoint 3: 64 bytes Ping-pong Mode (two memory banks) for bulk endpoints * Suspend/resume logic 8-channel ADC 10-bit 100 Ksamples/sec. Successive Approximation Register ADC -2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs Analog-to-digital Converter * * * * 28 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * * * Individual enable and disable of each channel External voltage reference for better accuracy on low voltage inputs Multiple trigger source - - - * - * Hardware or software trigger External trigger pin Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels Sleep Mode and conversion sequencer Four of eight analog inputs shared with digital signals 29 6070A-ATARM-28-Oct-04 30 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary ARM7TDMI Processor Overview Overview The ARM7TDMI core executes both the 32-bit ARM (R) and 16-bit Thumb(R) instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7tDMI processor are: * * ARM7TDMI Based on ARMv4T Architecture Two Instruction Sets - - * - - - ARM(R) High-performance 32-bit Instruction Set Thumb(R) High Code Density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E) Three-Stage Pipeline Architecture 31 6070A-ATARM-28-Oct-04 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) Instruction Type Data Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where. ARM7TDMI Operating Mode The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources. ARM7TDMI Registers The ARM7TDMI processor has a total of 37registers: * * 31 general-purpose 32-bit registers 6 status registers These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer 32 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary . Table 6. ARM7TDMI ARM Modes and Registers Layout User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. 33 6070A-ATARM-28-Oct-04 A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: * * * * four ALU flags (Negative, Zero, Carry, and Overflow) two interrupt disable bits (one for each type of interrupt) one bit to indicate ARM or Thumb execution five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. Exception Types The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of exceptions are: * * * * * fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: * * by using a data-processing instruction with the S-bit set, and the PC as the destination by using the Load Multiple with Restore CPSR instruction (LDM) ARM Instruction Set Overview The ARM instruction set is divided into: * * * * * * Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 7 gives the ARM instruction mnemonic list. 34 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 7. ARM Instruction Mnemonic List Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Mnemonic CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC Operation Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: * * * * * Branch instructions Data processing instructions Load and Store instructions Load and Store Multiple instructions Exception-generating instruction In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) 35 6070A-ATARM-28-Oct-04 and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 8 gives the Thumb instruction mnemonic list. Table 8. Thumb Instruction Mnemonic List Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right BL SWI STR STRH STRB LDRSB STMIA POP Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack 36 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AT91SAM7S64 Debug and Test Features Description The AT91SAM7S64 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. Block Diagram Figure 10. Debug and Test Block Diagram TMS TCK TDI Boundary TAP ICE/JTAG TAP JTAGSEL TDO ICE Reset and Test POR TST ARM7TDMI PIO DTXD DRXD PDC DBGU 37 6070A-ATARM-28-Oct-04 Application Examples Debug Environment Figure 11 on page 38 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 11. Application Debug Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM7Sxx RS232 Connector Terminal AT91SAM7Sxx-based Application Board 38 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Test Environment Figure 12 on page 39 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM7Sxx Chip 1 AT91SAM7Sxx-based Application Board In Test Debug and Test Pin Description Table 9. Debug and Test Pin List Pin Name Function Reset/Test NRST TST Microcontroller Reset Test Mode Select ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Input Input Output Input Input Input/Output Input Low High Type Active Level 39 6070A-ATARM-28-Oct-04 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: * In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor. Embedded Incircuit Emulator * There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B). Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. The Debug Unit can be used to upload an application into the internal SRAM. It is activated by the boot program when no valid application is detected. The protocol used to load the application is XMODEM. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7S64 Debug Unit Chip ID value is 0x27090540 on 32-bit width. For further details on the Debug Unit, see"Debug Unit (DBGU)" on page 179. IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. 40 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associated control signals. Each AT91SAM7S64 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 10. AT91SAM7S64 JTAG Boundary Scan Register Bit Number 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 PA13/PGMD1 IN/OUT PA14/PGMD2 IN/OUT PA15/PGM3 IN/OUT PA16/PGMD4 IN/OUT PA20/PGMD8/AD3 IN/OUT PA19/PGMD7/AD2 IN/OUT PA21/PGMD9 IN/OUT PA18/PGMD6/AD1 IN/OUT PA17/PGMD5/AD0 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL 41 6070A-ATARM-28-Oct-04 Table 10. AT91SAM7S64 JTAG Boundary Scan Register (Continued) Bit Number 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PA5/PGMRDY IN/OUT PA6/PGMNOE IN/OUT PA7/PGMNVALID IN/OUT PA8/PGMM0 IN/OUT PA9/PGMM1 IN/OUT PA10/PGMM2 IN/OUT PA11/PGMM3 IN/OUT PA12/PGMD0 IN/OUT PA24/PGMD12 IN/OUT PA23/PGMD11 IN/OUT PA22/PGMD10 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL 42 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 10. AT91SAM7S64 JTAG Boundary Scan Register (Continued) Bit Number 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PA30 IN/OUT PA29 IN/OUT PA0/PGMEN0 IN/OUT PA1/PGMEN1 IN/OUT PA2 IN/OUT PA3 IN/OUT PA28 IN/OUT PA27/PGMD15 IN/OUT PA26/PGMD14 IN/OUT PA25/PGMD13 IN/OUT PA4/PGMNCMD IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL 43 6070A-ATARM-28-Oct-04 Table 10. AT91SAM7S64 JTAG Boundary Scan Register (Continued) Bit Number 3 2 1 0 ERASE IN PA31 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 VERSION[31:28]: Product Version Number Set to 0x1. PART NUMBER[27:12]: Product Part Number Set to 0x5B06. MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 05B0_603F. 44 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Reset Controller (RSTC) Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. Block Diagram Figure 13. Reset Controller Block Diagram Reset Controller bod_rst_en brown_out Brownout Manager bod_reset Main Supply POR Startup Counter Reset State Manager rstc_irq proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset WDRPROC wd_fault SLCK 45 6070A-ATARM-28-Oct-04 Functional Description The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: * * * proc_nreset: Processor reset line. It also resets the Watchdog Timer. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14 shows the block diagram of the NRST Manager. Figure 14. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 s and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. 46 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read. The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 15. Brownout Manager bod_rst_en bod_reset RSTC_MR BODIEN RSTC_SR brown_out BODSTS Other interrupt sources rstc_irq 47 6070A-ATARM-28-Oct-04 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device. The startup time, as shown in Figure 16, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset. When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Power-up Reset Figure 16. Power-up Reset SLCK MCK Main Supply POR output proc_nreset periph_nreset Any Freq. Startup Time Processor Startup = 3 cycles NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 48 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. Th e NR ST Man age r gua rante es th at the NR ST line is asser te d for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 17. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 49 6070A-ATARM-28-Oct-04 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. Figure 18. Brownout Reset State SLCK MCK brown_out or bod_reset Resynch. 2 cycles Processor Startup = 3 cycles Any Freq. proc_nreset RSTTYP periph_nreset Any XXX 0x5 = Brownout Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 50 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: * * PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). * The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 19. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 51 6070A-ATARM-28-Oct-04 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: * If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted. * The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 20. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 52 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: * * * * * * Power-up Reset Brownout Reset Watchdog Reset Software Reset User Reset When in User Reset: - - * - - * - - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated. A watchdog event has priority over the current state. The NRST has no effect. The processor reset is active and so a Software Reset cannot be programmed. A User Reset cannot be entered. Particular cases are listed below: When in Software Reset: When in Watchdog Reset: Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: * * RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 21). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. * * * 53 6070A-ATARM-28-Oct-04 Figure 21. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 54 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Reset Controller (RSTC) User Interface Table 11. Reset Controller Registers Offset 0x00 0x04 0x08 Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000 55 6070A-ATARM-28-Oct-04 Reset Controller Control Register Register Name: RSTC_CR Access Type: 31 Write-only 30 29 28 KEY 27 26 25 24 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 EXTRST 18 - 10 - 2 PERRST 17 - 9 16 - 8 - 0 PROCRST 1 - * PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. * PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. * EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 56 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Reset Controller Status Register Register Name: RSTC_SR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 25 - 17 SRCMP 9 RSTTYP 1 BODSTS 24 - 16 NRSTL 8 2 - 0 URSTS * URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. * BODSTS: Brownout Detection Status 0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR. * RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset Comments VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low BrownOut reset occurred * NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). * SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 57 6070A-ATARM-28-Oct-04 Reset Controller Mode Register Register Name: RSTC_MR Access Type: 31 Read/Write 30 29 28 KEY 27 26 25 24 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 20 - 12 - 4 URSTIEN 19 - 11 18 - 10 ERSTL 17 - 9 16 BODIEN 8 3 - 2 - 1 - 0 URSTEN * URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. * URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. * BODIEN: Brownout Detection Interrupt Enable 0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq. * ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2 (ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 s and 2 seconds. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 58 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Real-time Timer (RTT) Overview Block Diagram Figure 22. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 59 6070A-ATARM-28-Oct-04 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is reached by writing RTPRES at 1. In this case, the period of the signal provided to the Real-time Timer counter is 30.52 s (when Slow Clock is 32.768 Hz) and the maximum the Real-time Timer can cover is 131072 seconds, corresponding to more than 36 days. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm reg ister is se t to its ma ximum value, co rrespo nding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 60 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 23. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 61 6070A-ATARM-28-Oct-04 Real-time Timer (RTT) User Interface Table 12. Real-time Timer Register Mapping Offset 0x00 0x04 0x08 0x0C Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 62 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Real-time Timer Mode Register Register Name: RTT_MR Access Type: 31 - 23 - 15 Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RTPRES 27 - 19 - 11 26 - 18 RTTRST 10 25 - 17 RTTINCIEN 9 24 - 16 ALMIEN 8 7 6 5 4 RTPRES 3 2 1 0 * RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The Prescaler Period is equal to 216 RTPRES 0: The Prescaler Period is equal to RTPRES. * ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. * RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. * RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 63 6070A-ATARM-28-Oct-04 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: 31 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 * ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 64 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Real-time Timer Value Register Register Name: RTT_VR Access Type: 31 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 * CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 65 6070A-ATARM-28-Oct-04 Real-time Timer Status Register Register Name: RTT_SR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RTTINC 24 - 16 - 8 - 0 ALMS * ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. * RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 66 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Periodic Interval Timer (PIT) Overview The Periodic Interval Timer (PIT) provides the operating system's scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. Block Diagram Figure 24. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 67 6070A-ATARM-28-Oct-04 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 25 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 68 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 25. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 69 6070A-ATARM-28-Oct-04 Periodic Interval Timer (PIT) User Interface Table 13. Periodic Interval Timer (PIT) Register Mapping Offset 0x00 0x04 0x08 0x0C Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 70 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: 31 - 23 - 15 Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PIV 27 - 19 26 - 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 7 6 5 4 PIV 3 2 1 0 * PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). * PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. * PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 71 6070A-ATARM-28-Oct-04 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PITS * PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 72 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 73 6070A-ATARM-28-Oct-04 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 74 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Watchdog Timer (WDT) Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. Block Diagram Figure 26. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WV reload 1 0 WDRSTT 12-bit Down Counter WDT_MR reload WDD Current Value 1/128 SLCK <= WDD WDT_MR WDRSTEN =0 wdt_fault (to Reset Controller) set WDUNF set reset wdt_int WDERR read WDT_SR or reset reset WDFIEN WDT_MR 75 6070A-ATARM-28-Oct-04 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the "wdt_fault" signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur in a window defined by 0 and WDD in the WDT_MR: 0 WDT WDD; writing WDRSTT restarts the Watchdog Timer. Any attempt to restart the Watchdog Timer in the range [WDV; WDD] results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the "wdt_fault" signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal "wdt_fault" to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the "wdt_fault" signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. 76 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 27. Watchdog Behavior Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR = WDRSTT if WDRSTEN is 0 Watchdog Fault 77 6070A-ATARM-28-Oct-04 Watchdog Timer (WDT) User Interface Table 14. Watchdog Timer (WDT) Register Mapping Offset 0x00 0x04 0x08 Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read/Write Once Read-only Reset Value 0x3FFF_2FFF 0x0000_0000 78 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Watchdog Timer Control Register Register Name: WDT_CR Access Type: 31 Write-only 30 29 28 KEY 27 26 25 24 23 - 15 - 7 - 22 - 14 - 6 - 21 - 13 - 5 - 20 - 12 - 4 - 19 - 11 - 3 - 18 - 10 - 2 - 17 - 9 - 1 - 16 - 8 - 0 WDRSTT * WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 79 6070A-ATARM-28-Oct-04 Watchdog Timer Mode Register Register Name: WDT_MR Access Type: 31 Read / Write Once 30 29 WDIDLEHLT 21 28 WDDBGHLT 20 WDD 27 26 WDD 19 18 17 16 25 24 23 22 15 WDDIS 7 14 WDRPROC 6 13 WDRSTEN 5 12 WDFIEN 4 WDV 11 10 WDV 9 8 3 2 1 0 * WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. * WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt. * WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset. * WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset. * WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error. * WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. * WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. * WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. 80 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Watchdog Timer Status Register Register Name: WDT_SR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WDERR 24 - 16 - 8 - 0 WDUNF * WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR. * WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR. 81 6070A-ATARM-28-Oct-04 82 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Voltage Regulator Mode Controller (VREG) Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode. Voltage Regulator Power Controller (VREG) User Interface Table 15. Voltage Regulator Power Controller Register Mapping Offset 0x60 Register Voltage Regulator Mode Register Name VREG_MR Access Read/Write Reset Value 0x0 Voltage Regulator Mode Register Register Name: VREG_MR Access Type: 31 - 23 - 15 - 7 - Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PSTDBY * PSTDBY: Periodic Interval Value 0 = Voltage regulator in normal mode. 1 = Voltage regulator in standby mode (low-power mode). 83 6070A-ATARM-28-Oct-04 84 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Memory Controller (MC) Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral Data Controller. It features a simple bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. Block Diagram Figure 28. Memory Controller Block Diagram Memory Controller ASB ARM7TDMI Processor Embedded Flash Controller Abort Status Internal RAM Internal Flash Abort Bus Arbiter Misalignment Detector Address Decoder User Interface Peripheral Data Controller Peripheral 0 Peripheral 1 APB Bridge APB From Master to Slave Peripheral N 85 6070A-ATARM-28-Oct-04 Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters. It is made up of: * * * * * A bus arbiter An address decoder An abort status A misalignment detector An Embedded Flash Controller The MC handles only little-endian mode accesses. The masters work in little-endian mode only. Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the two masters. The Peripheral Data Controller has the highest priority; the ARM processor has the lowest one. The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines three separate areas: * * * One 256-Mbyte address space for the internal memories One 256-Mbyte address space reserved for the embedded peripherals An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if accessed Address Decoder Figure 29 shows the assignment of the 256-Mbyte memory areas. Figure 29. Memory Areas 256M Bytes 0x0000 0000 0x0FFF FFFF 0x1000 0000 Internal Memories 14 x 256MBytes 3,584 Mbytes Undefined (Abort) 0xEFFF FFFF 256M Bytes 0xF000 0000 0xFFFF FFFF Peripherals 86 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory. When the address of the access is undefined within the internal memory area, the Address Decoder returns an Abort to the master. Figure 30. Internal Memory Mapping 0x0000 0000 Internal Memory Area 0 0x000F FFFF 1M Bytes 0x0010 0000 0x001F FFFF Internal Memory Area 1 Internal Flash Internal Memory Area 2 Internal SRAM 1M Bytes 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 1M Bytes Undefined Areas (Abort) 253M bytes 0x0FFF FFFF Internal Memory Area 0 The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0. Before execution of the remap command, the on-chip Flash is mapped into Internal Memory Area 0, so that the ARM7TDMI reaches an executable instruction contained in Flash. After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its original location and at address 0x0. Remap Command After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0. As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control. The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap Control Register) RCB field to one. The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset. 87 6070A-ATARM-28-Oct-04 Abort Status There are three reasons for an abort to occur: * * access to an undefined address an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral Data Controller does not handle the abort input signal. Note that the connection is not represented in Figure 28. To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set. The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include: * * * * * the size of the request (field ABTSZ) the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP) whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit MISADD) the source of the access leading to the last abort (bits MST0 and MST1) whether or not an abort occurred for each master since the last read of the register (bit SVMST0 and SVMST1) unless this information is loaded in MST bits In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context. In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM processor. Embedded Flash Controller The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands. The Memory Controller features a Misalignment Detector that checks the consistency of the accesses. For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructions are not checked. The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase. As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bug is simplified. Misalignment Detector 88 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 16. Memory Controller (MC) Register Mapping Offset 0x00 0x04 0x08 0x0C-0x5C 0x60 Register MC Remap Control Register MC Abort Status Register MC Abort Address Status Register Reserved EFC Configuration Registers Name MC_RCR MC_ASR MC_AASR - Access Write-only Read-only Read-only - 0x0 0x0 - Reset State See "Embedded Flash Controller (EFC)" on page 93. 89 6070A-ATARM-28-Oct-04 MC Remap Control Register Register Name: Access Type: Offset: 31 - 23 - 15 - 7 - MC_RCR Write-only 0x00 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RCB * RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 90 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary MC Abort Status Register Register Name: Access Type: Reset Value: Offset: 31 - 23 - 15 - 7 - MC_ASR Read-only 0x0 0x04 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 3 - 27 - 19 - 11 ABTTYP 2 - 1 MISADD 26 - 18 - 10 25 SVMST1 17 MST1 9 ABTSZ 0 UNDADD 24 SVMST0 16 MST0 8 * UNDADD: Undefined Address Abort Status 0: The last abort was not due to the access of an undefined address in the address space. 1: The last abort was due to the access of an undefined address in the address space. * MISADD: Misaligned Address Abort Status 0: The last aborted access was not due to an address misalignment. 1: The last aborted access was due to an address misalignment. * ABTSZ: Abort Size Status. ABTSZ 0 0 1 1 0 1 0 1 Abort Size Byte Half-word Word Reserved * ABTTYP: Abort Type Status. ABTTYP 0 0 1 1 0 1 0 1 Abort Type Data Read Data Write Code Fetch Reserved * MST0: ARM7TDMI Abort Source 0: The last aborted access was not due to the ARM7TDMI. 1: The last aborted access was due to the ARM7TDMI. * MST1: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. 91 6070A-ATARM-28-Oct-04 * SVMST0: Saved ARM7TDMI Abort Source 0: No abort due to the ARM7TDMI occurred since the last read of MC_ASR or it is notified in the bit MST0. 1: At least one abort due to the ARM7TDMI occurred since the last read of MC_ASR. * SVMST1: Saved PDC Abort Source 0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST1. 1: At least one abort due to the PDC occurred since the last read of MC_ASR. MC Abort Address Status Register Register Name: Access Type: Reset Value: Offset: 31 MC_AASR Read-only 0x0 0x08 30 29 28 ABTADD 27 26 25 24 23 22 21 20 ABTADD 19 18 17 16 15 14 13 12 ABTADD 11 10 9 8 7 6 5 4 ABTADD 3 2 1 0 * ABTADD: Abort Address This field contains the address of the last aborted access. 92 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Embedded Flash Controller (EFC) Overview The Embedded Flash Controller (EFC) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. Functional Description Embedded Flash Organization The Embedded Flash interfaces directly to the 32-bit internal bus. It is composed of several interfaces: * * * One memory plane organized in several pages of the same size Two 32-bit read buffers used for code read optimization. (See "Read Operations" on page 95.) One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is write-only and accessible all along the 1 MByte address space, so that each word can be written to its final address. (See "Write Operations" on page 97.) Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Several general-purpose NVM bits. Each bit controls a specific feature in the device. Refer to the product definition section to get the GP NVM assignment. * * The Embedded Flash size, the page size and the lock region organization are described in the product definition section. 93 6070A-ATARM-28-Oct-04 Figure 31. Embedded Flash Memory Mapping Page 0 Flash Memory Start Address Lock Region 0 Lock Region 1 Lock Bit 0 Lock Bit 1 Page (m-1) Lock Region (n-1) 32-bit wide Lock Bit n-1 Page ( (n-1)*m ) Page (n*m-1) 94 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Read Operations An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in Thumb mode (16-bit instruction set). See Figure 32, Figure 33 and Figure 34. This optimization concerns only Code Fetch and not Data. The read operations can be performed with or without wait state. Up to 3 wait states can be programmed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see "MC Flash Mode Register" on page 103). Defining FWS to be 0 enables the single-cycle access of the embedded Flash. The Flash memory is accessible through 8-, 16- and 32-bit reads. As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash wraps around the address space and appears to be repeated within it. Figure 32. Code Read Optimization in Thumb Mode for FWS = 0 Master Clock ARM Request (16-bit) Code Fetch @Byte 0 Flash Access @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14 @Byte 16 Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Bytes 16-19 Buffer (32 bits) Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Data To ARM Bytes 0-1 Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11 Bytes 12-13 Bytes 14-15 Note: When FWS is equal to 0, all accesses are performed in a single-cycle access. 95 6070A-ATARM-28-Oct-04 Figure 33. Code Read Optimization in Thumb Mode for FWS = 1 1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle 1 Wait State Cycle Master Clock ARM Request (16-bit) Code Fetch @Byte 0 Flash Access @Byte 2 @Byte 4 @Byte 6 @Byte 8 @Byte 10 @Byte 12 @Byte 14 Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Buffer (32 bits) Bytes 0-3 Bytes 4-7 Bytes 8-11 Data To ARM Bytes 0-1 Bytes 2-3 Bytes 4-5 Bytes 6-7 Bytes 8-9 Bytes 10-11 Bytes 12-13 Note: When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the first one). Figure 34. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles Master Clock ARM Request (16-bit) Code Fetch @Byte 0 @2 @4 @6 @8 @10 @12 Flash Access Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Buffer (32 bits) Bytes 0-3 Bytes 4-7 Bytes 8-11 Data To ARM 0-1 2-3 4-5 6-7 8-9 10-11 12-13 Note: When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the third access FWS cycles, the fourth access one cycle, etc. 96 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Write Operations The internal memory area reserved for the embedded Flash can also be written through a write-only latch buffer. Write operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area address space and appear to be repeated 1024 times within it. Write operations can be prevented by programming the Memory Protection Unit of the product. Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data Fcorruption. Write operations are performed in the number of wait states equal to the number of wait states for read operations + 1, except for FWS = 3 (see "MC Flash Mode Register" on page 103). Flash Commands The Embedded Flash Controller offers a command set to manage programming the memory flash, locking and unlocking lock sectors, consecutive programming and locking, and full Flash erasing. Table 17. Set of Commands Command Write page Set Lock Bit Write Page and Lock Clear Lock Bit Erase all Set General-purpose NVM Bit Clear General-purpose NVM Bit Set Security Bit Value 0x01 0x02 0x03 0x04 0x08 0x0B 0x0D 0x0F Mnemonic WP SLB WPL CLB EA SGPB CGPB SSB To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. All the commands are protected by the same keyword, which has to be written in the eight highest bits of the MC_FCR register. Writing MC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the memory plane; however, the PROGE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. When the current command writes or erases a page in a locked region, the command has no effect on the whole memory plane; however, the FLOCKE flag is set in the MC_FSR register. This flag is automatically cleared by a read access to the MC_FSR register. 97 6070A-ATARM-28-Oct-04 Figure 35. Command Statechart Read Status: MC_FSR No Check if FRDY flag set Yes Write FCMD and PAGENB in MC_FCR Read Status: MC_FSR No Check if FRDY flag set Yes Check if LOCKE flag set Yes Locking region violation No Check if PROGE flag set Yes Bad keyword violation and/or Invalid command No Command Successful In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) in the Flash Mode Register MC_FMR must be correctly programmed (see "MC Flash Mode Register" on page 103). Note: This field defines the number of Master Clock cycles in 1 microsecond that allow completion of some necessary internal timings. Flash Programming Several commands can be used to program the Flash. The Flash technology requires that an erase must be done before programming. The entire memory plane can be erased at the same time, or a page can be automatically erased by clearing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR register. 98 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps if it has been erased before (see Figure 36). Figure 36. Example of Partial Page Programming: 32 bits wide 32 bits wide 32 bits wide FF FF FF FF 16 words ... FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CA CA CA FF FF FF FF FF FF FF FF FF FE FE FE FF FF FF FF FF FF ... FF FF FF FF FF FF FE FE FE FF FF FF FF FF FF FF FF FF CA CA CA DE DE DE FF FF FF FF FF FF FE FF FF FF FF ... FF FF CA ... CA CA ... DE DE DE ... FF FF FF FF FF FF FE FE FE CA CA CA FF FF FF 16 words FF FF FF FF FF ... FF FF FF FF FF FF ... FF FF FF FF FF FF ... FF FF FF FF ... CA CA CA FE FE CA CA CA FF FF FF ... FF FF FF 16 words FF FF FF ... FF FF FF 16 words FF FF Step 1. Erase All Flash Page 7 erased Step 2. Programming of the second part of Page 7 (NEBP = 1) Step 3. Programming of the third part of Page 7 (NEBP = 1) After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences. The lock bit can be automatically set after page programming using WPL. Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The latch buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption. Data are written to the latch buffer before the programming command is written to the Flash Command Register MC_FCR. The sequence is as follows: * * Write the full page, at any page address, within the internal memory area address space using only 32-bit access. Programming starts as soon as the page number and the programming command are written to the Flash Command Register. The FRDY bit in the Flash Programming Status Register (MC_FSR) is automatically cleared. When programming is completed, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt was enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. Lock Error: The page to be programmed belongs to a locked region. A command must be previously run to unlock the corresponding region. * Two errors can be detected in the MC_FSR register after a programming sequence: * * 99 6070A-ATARM-28-Oct-04 Erase All Command The entire memory can be erased if the Erase All Command (EA) in the Flash Command Register MC_FCR is written. Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written at 1 in MC_FMR, the interrupt line rises. When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Two errors can be detected in the MC_FSR register after a programming sequence: * * Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register. Lock Error: At least one lock region to be erased is protected. The erase command has been refused and no page has been erased. A Clear Lock Bit command must be executed previously to unlock the corresponding lock regions. Lock Bit Protection Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the embedded Flash memory plane. They prevent writing/erasing protected pages. After production, the device may have some embedded Flash lock regions locked. These locked regions are reserved for a default application. Refer to the product definition section for the default embedded Flash mapping. Locked sectors can be unlocked to be erased and then programmed with another application or other data. The lock sequence is: * The Flash Command register must be written with the following value: (0x5A << 24) | (lockPageNumber << 8 & PAGEN) | SLB lockPageNumber is a page of the corresponding lock region. When locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. * A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register, may be detected in the MC_FSR register after a programming sequence. It is possible to clear lock bits that were set previously. Then the locked region can be erased or programmed. The unlock sequence is: * The Flash Command register must be written with the following value: (0x5A << 24) | (lockPageNumber << 8 & PAGEN) | CLB lockPageNumber is a page of the corresponding lock region. When the unlock completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. * A programming error, where a bad keyword and/or an invalid command have been written in the MC_FCR register, may be detected in the MC_FSR register after a programming sequence. The Unlock command programs the lock bit to 1; the corresponding bit LOCKSx in MC_FSR reads 0. The Lock command programs the lock bit to 0; the corresponding bit LOCKSx in MC_FSR reads 1. Note: Access to the Flash in Read Mode is permitted when a Lock or Unlock command is performed. 100 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. These general-purpose bits are dedicated to protect other parts of the product. They can be set (activated) or cleared individually. Refer to the product definition section for the general-purpose NVM bit action. The activation sequence is: * Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register with the SEL command and the number of the general-purpose bit to be set in the PAGEN field. When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register If the general-purpose bit number is greater than the total number of general-purpose bits, then the command has no effect. Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN field. When the clear completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. Programming Error: a bad keyword and/or an invalid command have been written in the MC_FCR register If the number of the general-purpose bit set in the PAGEN field is greater than the total number of general-purpose bits, then the command has no effect. * Two errors can be detected in the MC_FSR register after a programming sequence: * * It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is: * * Two errors can be detected in the MC_FSR register after a programming sequence: * * The Clear General-purpose Bit command programs the general-purpose NVM bit to 1; the corresponding bit GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command programs the general-purpose NVM bit to 0; the corresponding bit GPNVMx in MC_FSR reads 1. Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is performed. Security Bit The goal of the security bit is to prevent external access to the internal bus system. JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set, this bit can be reset only by an external hardware ERASE request to the chip. Refer to the product definition section for the pin name that controls the ERASE. In this case, the full memory plane is erased and all lock and general-purpose NVM bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The activation sequence is: * * Start the Set Security Bit command (SSB) by writing the Flash Command Register. When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set. 101 6070A-ATARM-28-Oct-04 Embedded Flash Controller (EFC) User Interface The User Interface of the Embedded Flash Controller is integrated within the Memory Controller. Base Address: 0xFFFF FF00 Table 18. Embedded Flash Controller (EFC) Register Mapping Offset 0x60 0x64 0x68 0x6C Register MC Flash Mode Register MC Flash Command Register MC Flash Status Register Reserved Name MC_FMR MC_FCR MC_FSR - Access Read/Write Write-only Read-only - Reset State 0x0 - - - 102 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary MC Flash Mode Register Register Name: Access Type: Offset: 31 - 23 MC_FMR Read/Write 0x60 30 - 22 29 - 21 28 - 20 FMCN 27 - 19 26 - 18 25 - 17 24 - 16 15 - 7 NEBP 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 PROGE 10 - 2 LOCKE 9 FWS 1 - 8 0 FRDY * FRDY: Flash Ready Interrupt Enable 0 = Flash Ready does not generate an interrupt. 1 = Flash Ready generates an interrupt. * LOCKE: Lock Error Interrupt Enable 0 = Lock Error does not generate an interrupt. 1 = Lock Error generates an interrupt. * PROGE: Programming Error Interrupt Enable 0 = Programming Error does not generate an interrupt. 1 = Programming Error generates an interrupt. * NEBP: No Erase Before Programming 0 = A page erase is performed before programming. 1 = No erase is performed before programming. * FWS: Flash Wait State This field defines the number of wait states for read and write operations: FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Write Operations 2 cycles 3 cycles 4 cycles 4 cycles * FMCN: Flash Microsecond Cycle Number This field defines the number of Master Clock cycles in 1 microsecond. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds. Warning: In order to guarantee valid operations on the Flash memory, the field Flash Microsecond Cycle Number (FMCN) must be correctly programmed. 103 6070A-ATARM-28-Oct-04 MC Flash Command Register Register Name: Access Type: Offset: 31 MC_FCR Write-only 0x64 30 29 28 KEY 27 26 25 24 23 - 15 22 - 14 21 - 13 20 - 12 PAGEN 19 - 11 18 - 10 17 PAGEN 9 16 8 7 - 6 - 5 - 4 - 3 2 FCMD 1 0 * FCMD: Flash Command This field defines the Flash commands: FCMD 0000 0001 0010 0011 Operations No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR. Write Page Command (WP): Starts the programming of the page specified in the PAGEN field. Set Lock Bit Command (SLB): Starts a set lock bit sequence of the lock region specified in the PAGEN field. Write Page and Lock Command (WPL): The lock sequence of the lock region associated with the page specified in the field PAGEN occurs automatically after completion of the programming sequence. Clear Lock Bit Command (CLB): Starts a clear lock bit sequence of the lock region specified in the PAGEN field. Erase All Command (EA): Starts the erase of the entire Flash. If at least one page is locked, the command is cancelled. Set General-purpose NVM Bit (SGPB): Activates the general-purpose NVM bit corresponding to the number specified in the PAGEN field. Clear General Purpose NVM Bit (CGPB): Deactivates the general-purpose NVM bit corresponding to the number specified in the PAGEN field. Set Security Bit Command (SSB): Sets security bit. Reserved. Raises the Programming Error Status flag in the Flash Status Register MC_FSR. 0100 1000 1011 1101 1111 Others 104 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * PAGEN: Page Number Command Write Page Command Write Page and Lock Command Erase All Command Set/Clear Lock Bit Command Set/Clear General Purpose NVM Bit Command Set Security Bit Command Note: PAGEN Description PAGEN defines the page number to be written. PAGEN defines the page number to be written and its associated lock region. This field is meaningless PAGEN defines one page number of the lock region to be locked or unlocked. PAGEN defines the general-purpose bit number. This field is meaningless Depending on the command, all the possible unused bits of PAGEN are meaningless. * KEY: Write Protection Key This field should be written with the value 0x5A to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 105 6070A-ATARM-28-Oct-04 MC Flash Status Register Register Name: Access Type: Offset: 31 LOCKS15 23 LOCKS7 15 - 7 - MC_FSR Read-only 0x68 30 LOCKS14 22 LOCKS6 14 - 6 - 29 LOCKS13 21 LOCKS5 13 - 5 - 28 LOCKS12 20 LOCKS4 12 - 4 SECURITY 27 LOCKS11 19 LOCKS3 11 - 3 PROGE 26 LOCKS10 18 LOCKS2 10 - 2 LOCKE 25 LOCKS9 17 LOCKS1 9 GPNVM1 1 - 24 LOCKS8 16 LOCKS0 8 GPNVM0 0 FRDY * FRDY: Flash Ready Status 0 = The Embedded Flash Controller is busy and the application must wait before running a new command. 1 = The Embedded Flash Controller is ready to run a new command. * LOCKE: Lock Error Status 0 = No programming of at least one locked lock region has happened since the last read of MC_FSR. 1 = Programming of at least one locked lock region has happened since the last read of MC_FSR. * PROGE: Programming Error Status 0 = No invalid commands and no bad keywords were written in the Flash Command Register MC_FCR. 1 = An invalid command and/or a bad keyword was/were written in the Flash Command Register MC_FCR. * SECURITY: Security Bit Status 0 = The security bit is disactive. 1 = The security bit is active. * GPNVMx: General-purpose NVM Bit Status 0 = The corresponding general-purpose NVM bit is disactive. 1 = The corresponding general-purpose NVM bit is active. * LOCKSx: Lock Region x Lock Status 0 = The corresponding lock region is not locked. 1 = The corresponding lock region is locked. 106 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Fast Flash Programming Interface (FFPI) Overview The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol. It offers an optimized access to all the embedded Flash functionalities. Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode is not designed for in-situ programming. 107 6070A-ATARM-28-Oct-04 Parallel Fast Flash Programming Device Configuration In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. Other pins must be left unconnected. Figure 37. Parallel Programming Interface VDDIO VDDIO VDDIO GND NCMD RDY NOE NVALID MODE[3:0] DATA[15:0] 0 - 50MHz TST PGMEN0 PGMEN1 PGMEN2 PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] XIN VDDCORE VDDIO VDDPLL VDDFLASH GND Table 19. Signal Description List Signal Name Function Power VDDFLASH VDDIO VDDCORE VDDPLL GND Flash Power Supply I/O Lines Power Supply Core Power Supply Backup I/O Lines Power Supply Ground Clocks XIN Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator. Test TST PGMEN0 PGMEN1 PGMEN2 Test Mode Select Test Mode Select Test Mode Select Test Mode Select Input Input Input Input High High High Low Must be connected to VDDIO Must be connected to VDDIO Must be connected to VDDIO Must be connected to GND Input 32KHz to 50MHz Power Power Power Power Ground Type Active Level Comments 108 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 19. Signal Description List (Continued) Signal Name Function PIO PGMNCMD PGMRDY PGMNOE PGMNVALID PGMM[3:0] PGMD[15:0] Valid command available 0: Device is busy 1: Device is ready for a new command Output Enable (active high) 0: DATA[15:0] is in input mode 1: DATA[15:0] is in output mode Specifies DATA type (See Table 20) Bi-directional data bus Input Output Input Output Input Input/Output Low High Low Low Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Type Active Level Comments Signal Names Depending on the MODE settings, DATA is latched in different internal registers. Table 20. Mode Coding MODE[3:0] 0000 0001 0010 0011 0100 0101 Default Symbol CMDE ADDR0 ADDR1 ADDR2 ADDR2 DATA IDLE Address Register MSBs Data Register No register Data Command Register Address Register LSBs When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 21. Command Bit Coding DATA[15:0] 0x0011 0x0012 0x0022 0x0032 0x0042 0x0013 0x0014 0x0024 0x0015 0x0034 0x0044 0x0025 Symbol READ WP WPL EWP EWPL EA SLB CLB GLB SFB CFB GFB Command Executed Read Flash Write Page Flash Write Page and Lock Flash Erase Page and Write Page Erase Page and Write Page then Lock Erase All Set Lock Bit Clear Lock Bit Get Lock Bit Set General Purpose NVM bit Clear General Purpose NVM bit Get General Purpose NVM bit 109 6070A-ATARM-28-Oct-04 Table 21. Command Bit Coding (Continued) DATA[15:0] 0x0054 0x0035 0x001E Symbol SSE GSE GVE Command Executed Set Security Bit Get Security Bit Get Version Entering Programming Mode The following algorithm puts the device in Parallel Programming Mode: * * * * Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. Apply XIN clock within TPOR_RESET if an external clock is available. Wait for TPOR_RESET Start a read or write handshaking. After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer handshake. Note: Programmer Handshaking An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD signal is high and RDY is high. For details on the write handshaking sequence, refer to Figure 38 and Table 22. Figure 38. Parallel Programming Timing, Write Sequence Write Handshaking NCMD RDY 2 3 4 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 22. Write Handshake Step 1 2 3 Programmer Action Sets MODE and DATA signals Clears NCMD signal Waits for RDY low Device Action Waits for NCMD low Latches MODE and DATA Clears RDY signal Data I/O Input Input Input 110 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 22. Write Handshake (Continued) Step 4 5 6 Programmer Action Releases MODE and DATA signals Sets NCMD signal Waits for RDY high Device Action Executes command and polls NCMD high Executes command and polls NCMD high Sets RDY Data I/O Input Input Input Read Handshaking For details on the read handshaking sequence, refer to Figure 39 and Table 23. Figure 39. Parallel Programming Timing, Read Sequence NCMD RDY 2 3 12 13 NOE NVALID 4 DATA[15:0] 1 MODE[3:0] ADDR Adress IN 5 7 6 Z 8 9 11 10 X IN Data OUT Table 23. Read Handshake Step 1 2 3 4 5 6 7 8 9 10 11 12 13 Reads value on DATA Bus Sets NOE signal Waits for NVALID high Sets DATA in ouput mode Sets NCMD signal Waits for RDY high Sets DATA bus in input mode Sets NVALID signal Waits for NCMD high Sets RDY signal Programmer Action Sets MODE and DATA signals Clears NCMD signal Waits for RDY low Sets DATA signal in tristate Clears NOE signal Waits for NVALID low Sets DATA bus in output mode and outputs the flash contents. Clears NVALID signal Waits for NOE high Device Action Waits for NCMD low Latch MODE and DATA Clears RDY signal Waits for NOE Low DATA I/O Input Input Input Input Tristate Output Output Output Output X Input Input Input 111 6070A-ATARM-28-Oct-04 Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21 on page 109. Each command is driven by the programmer through the parallel interface running several read/write handshaking sequences. When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a write automatically flushes the load buffer in the Flash. Flash Read Command This command is used to read the contents of the Flash memory. The read command can start at any valid address in the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer is automatically increased. Table 24. Read Command Step 1 2 3 4 5 6 7 ... n n+1 n+2 n+3 n+4 n+5 ... Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Read handshaking Read handshaking ... MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] READ 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: * * before access to any page other than the current one when a new command is validated (MODE = CMDE) The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 25. Write Command Step 1 2 3 4 Handshake Sequence Write handshaking Write handshaking Write handshaking Write handshaking MODE[3:0] CMDE ADDR0 ADDR1 ADDR2 DATA[15:0] WP or WPL or EWP or EWPL 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 112 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 25. Write Command (Continued) Step 5 6 7 ... n n+1 n+2 n+3 n+4 n+5 ... Handshake Sequence Write handshaking Write handshaking Write handshaking ... Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking Write handshaking ... MODE[3:0] ADDR3 DATA DATA ... ADDR0 ADDR1 ADDR2 ADDR3 DATA DATA ... DATA[15:0] 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... 32-bit Memory Address First byte 32-bit Flash Address 32-bit Flash Address 32-bit Flash Address Last Byte *Memory Address++ *Memory Address++ ... The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. Flash Full Erase Command This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase command is aborted and no page is erased. Table 26. Full Erase Command Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] EA 0 113 6070A-ATARM-28-Oct-04 Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first lock bit is activated. In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits are also cleared by the EA command. Table 27. Set and Clear Lock Bit Command Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] SLB or CLB Bit Mask Lock bits can be read using Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is set.. Table 28. Get Lock Bit Command Step 1 2 Handshake Sequence Write handshaking Read handshaking MODE[3:0] CMDE DATA DATA[15:0] GLB Lock Bit Mask Status 0 = Lock bit is cleared 1 = Lock bit is set Flash General Purpose NVM Commands General-purpose NVM bits (GP NVM bits) can be set using the Set Fuse command (SFB). This command also activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the first GP NVM bit is activated. In the same way, the Clear Fuse command (CFB) is used to clear general-purpose NVM bits. All the general-purpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactived when the corresponding bit in the pattern value is set to 1. Table 29. Set/Clear GP NVM Command Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] SFB or CFB GP NVM bit pattern value General-purpose NVM bits can be read using the Get Fuse Bit command (GFB). The nth GP NVM bit is active when bit n of the bit mask is set.. Table 30. Get GP NVM Bit Command Step 1 2 Handshake Sequence Write handshaking Read handshaking MODE[3:0] CMDE DATA DATA[15:0] GFB GP NVM Bit Mask Status 0 = GP NVM bit is cleared 1 = GP NVM bit is set 114 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Flash Security Bit Command A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 31. Set Security Bit Command Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] SSE 0 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 32. Get Version Command Step 1 2 Handshake Sequence Write handshaking Write handshaking MODE[3:0] CMDE DATA DATA[15:0] GVE Version 115 6070A-ATARM-28-Oct-04 Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 "Standard Test Access Port and Boundary-Scan Architecture". Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states. In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device. Device Configuration In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is significant. Other pins must be left unconnected. Figure 40. Serial Programming VDDIO VDDIO VDDIO GND TDI TDO TMS TCK TST PGMEN0 PGMEN1 PGMEN2 VDDCORE VDDIO VDDPLL VDDFLASH GND 0-50MHz XIN Table 33. Signal Description List Signal Name Function Power VDDFLASH VDDIO VDDCORE VDDPLL GND Flash Power Supply I/O Lines Power Supply Core Power Supply Backup I/O Lines Power Supply Ground Clocks XIN Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator. Input 32 kHz to 50 MHz Power Power Power Power Ground Type Active Level Comments 116 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 33. Signal Description List (Continued) Signal Name Function Test TST PGMEN0 PGMEN1 PGMEN2 Test Mode Select Test Mode Select Test Mode Select Test Mode Select JTAG TCK TDI TDO TMS JTAG TCK JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Input Input Output Input Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Input Input Input Input High High High Low Must be connected to VDDIO. Must be connected to VDDIO Must be connected to VDDIO Must be connected to GND Type Active Level Comments Entering Serial Programming Mode The following algorithm puts the device in Serial Programming Mode: * * * * * * * Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL. Apply XIN clock within TPOR_RESET + 32(TSCLK) if an external clock is available. Wait for TPOR_RESET. Reset the TAP controller clocking 5 TCK pulses with TMS set. Shift 0x2 into the IR register ( IR is 4 bits long, LSB first) without going through the RunTest-Idle state. Shift 0x2 into the DR register ( DR is 4 bits long, LSB first) without going through the RunTest-Idle state. Shift 0xC into the IR register ( IR is 4 bits long, LSB first) without going through the RunTest-Idle state. After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock. Else, XIN input is not considered. An higher frequency on XIN speeds up the programmer handshake. Note: Table 34. Reset TAP controller and go to Select-DR-Scan TDI X X X X X X Xt TMS 1 1 1 1 1 0 1 Test-Logic Reset Run-Test/Idle Select-DR-Scan TAP Controller State Read/Write Handshake Two registers of the device are accessible through the JTAG: * * Debug Comms Control Register: DCCR Debug Comms Data Register: DCDR 117 6070A-ATARM-28-Oct-04 Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit. The data to be written is scanned into the 32-bit data field with the address of the register to the 5-bit address field and 1 to the read/write bit. A register is read by scanning its address into the address field and 0 into the read/write bit, going through the UPDATE-DR TAP state, then scanning out the data. The 32-bit data field is ignored. Figure 41. TAP 8-bit DR Register TDI r/w 4 Address 5 0 31 Data 32 0 TDO Address Decoder Debug Comms Control Register Debug Comms Control Register A read or write takes place when the TAP controller enters UPDATE-DR state. * * The address of the Debug Comms Control Register is 0x04. The address of the Debug Comms Data Register is 0x05. The Debug Comms Control Register is read-only and allows synchronized handshaking between the processor and the debugger. * * Bit 1 (W): Denotes whether the programmer can read a data through the Debug Comms Data Register. If the device is busy W = 0, then the programmer must poll until W = 1. Bit 0 (R): Denotes whether the programmer can send data from the Debug Comms Data Register. If R = 1, data previously placed there through the scan chain has not been collected by the device and so the programmer must wait. Device Operations Several commands on the Flash memory are available. These commands are summarized in Table 21 on page 109. Commands are run by the programmer through the serial interface that is reading and writing the Debug Comms Registers. This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 35. Read Command Read/Write Write Write Read Read ... Read DR Data (Number of Words to Read) << 16 | READ Address Memory [address] Memory [address+4] ... Memory [address+(Number of Words to Read - 1)* 4] Flash Read Command 118 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Flash Write Command This command is used to write the Flash contents. The address transmitted must be a valid Flash address in the memory plane. The Flash memory plane is organized into several pages. Data to be written is stored in a load buffer that corresponds to a Flash memory page. The load buffer is automatically flushed to the Flash: * * before access to any page than the current one at the end of the number of words transmitted The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 36. Write Command Read/Write Write Write Write Write Write Write DR Data (Number of Words to Write) << 16 | (WP or WPL or EWP or EWPL) Address Memory [address] Memory [address+4] Memory [address+8] Memory [address+(Number of Words to Write - 1)* 4] Flash Write Page and Lock command (WPL) is equivalent to the Flash Write Command. However, the lock bit is automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using a Flash write and lock command. Flash Erase Page and Write command (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. Flash Erase Page and Write the Lock command (EWPL) combines EWP and WPL commands. Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 37. Full Erase Command Read/Write Write DR Data EA Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first lock bit and so on. In the same way, the Clear Lock command (CLB) is used to clear lock bits. All the lock bits can also be cleared by the EA command. 119 6070A-ATARM-28-Oct-04 Table 38. Set and Clear Lock Bit Command Read/Write Write Write DR Data SLB or CLB Bit Mask Lock bits can be read using Get Lock Bit command (GLB). When a bit set in the Bit Mask is returned, then the corresponding lock bit is active. Table 39. Get Lock Bit Command Read/Write Write Read DR Data GLB Bit Mask Flash Generalpurpose NVM Commands General-purpose NVM bits (GP NVM) can be set with the Set Fuse command (SFB). Using this command, several GP NVM bits can be activated at the same time. Bit 0 of Bit Mask corresponds to the first fuse bit and so on. In the same way, the Clear Fuse command (CFB) is used to clear GP NVM bits. All the general-purpose NVM bits are also cleared by the EA command. Table 40. Set and Clear General-purpose NVM Bit Command Read/Write Write Write DR Data SFB or CFB Bit Mask GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set. Table 41. Get General-purpose NVM Bit Command Read/Write Write Read DR Data GFB Bit Mask Flash Security Bit Command Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run. Only an event on the Erase pin can erase the security bit once the contents of the Flash have been erased. Table 42. Set Security Bit Command Read/Write Write DR Data SSE Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 43. Get Version Command Read/Write Write Read DR Data GVE Version 120 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Peripheral Data Controller (PDC) Overview The Peripheral Data Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral Data Contoller avoids processor intervention and removes the processor interrupthandling overhead. This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI. The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains: * * * * A 32-bit memory pointer register A 16-bit transfer count register A 32-bit register for next memory pointer A 16-bit register for next transfer count The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. Block Diagram Figure 42. Block Diagram Peripheral Peripheral Data Controller THR PDC Channel 0 RHR PDC Channel 1 Control Memory Controller Control Status & Control 121 6070A-ATARM-28-Oct-04 Functional Description Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter Registers (RCR, RNCR, TCR, and TNCR). The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and TXBUFE). ENDRX flag is set when the PERIPH_RCR register reaches zero. RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. ENDTX flag is set when the PERIPH_TCR register reaches zero. TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the peripheral status register. Memory Pointers Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC performs transfers using the new address. Transfer Counters There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transferring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, 122 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers. For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an interrupt request to the AIC. The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Register) is written. Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero. Data Transfers The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals. When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory. After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops. The same procedure is followed, in reverse, for transmit transfers. Priority of PDC Transfer Requests The Peripheral Data Controller handles transfer requests from the channel according to priorities fixed for each product.These priorities are defined in the product datasheet. If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 123 6070A-ATARM-28-Oct-04 Peripheral Data Controller (PDC) User Interface Table 44. Peripheral Data Controller (PDC) Register Mapping Offset Register Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Receive Next Pointer Register Receive Next Counter Register Transmit Next Pointer Register Transmit Next Counter Register PDC Transfer Control Register PDC Transfer Status Register Register Name PERIPH _RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR (1) Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Read-only Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc). 124 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PDC Receive Pointer Register Register Name: PERIPH_RPR Access Type: 31 Read/Write 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR * RXPTR: Receive Pointer Address Address of the next receive transfer. PDC Receive Counter Register Register Name: PERIPH_RCR Access Type: 31 Read/Write 30 29 28 27 26 25 24 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR * RXCTR: Receive Counter Value Number of receive transfers to be performed. 125 6070A-ATARM-28-Oct-04 PDC Transmit Pointer Register Register Name: PERIPH_TPR Access Type: 31 Read/Write 30 29 28 27 26 25 24 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR * TXPTR: Transmit Pointer Address Address of the transmit buffer. PDC Transmit Counter Register Register Name: PERIPH_TCR Access Type: 31 Read/Write 30 29 28 27 26 25 24 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR * TXCTR: Transmit Counter Value TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral data transfer is stopped. 126 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PDC Receive Next Pointer Register Register Name: PERIPH_RNPR Access Type: 31 Read/Write 30 29 28 27 26 25 24 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR 7 6 5 4 3 2 1 0 RXNPTR * RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. PDC Receive Next Counter Register Register Name: PERIPH_RNCR Access Type: 31 Read/Write 30 29 28 27 26 25 24 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 RXNCR 7 6 5 4 3 2 1 0 RXNCR * RXNCR: Receive Next Counter Value RXNCR is the size of the next buffer to receive. 127 6070A-ATARM-28-Oct-04 PDC Transmit Next Pointer Register Register Name: PERIPH_TNPR Access Type: 31 Read/Write 30 29 28 27 26 25 24 TXNPTR 23 22 21 20 19 18 17 16 TXNPTR 15 14 13 12 11 10 9 8 TXNPTR 7 6 5 4 3 2 1 0 TXNPTR * TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. PDC Transmit Next Counter Register Register Name: Access Type: 31 PERIPH_TNCR Read/Write 30 29 28 27 26 25 24 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 TXNCR 7 6 5 4 3 2 1 0 TXNCR * TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. 128 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PDC Transfer Control Register Register Name: PERIPH_PTCR Access Type: 31 Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXTDIS 1 TXTEN 0 - - - - - - RXTDIS RXTEN * RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set. * RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the receiver PDC transfer requests. * TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the transmitter PDC transfer requests. * TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the transmitter PDC transfer requests 129 6070A-ATARM-28-Oct-04 PDC Transfer Status Register Register Name: PERIPH_PTSR Access Type: 31 Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 TXTEN 0 - - - - - - - RXTEN * RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled. * TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled. 1 = Transmitter PDC transfer requests are enabled. 130 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Advanced Interrupt Controller (AIC) Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. Block Diagram Figure 43. Block Diagram FIQ IRQ0-IRQn AIC ARM Processor Up to Thirty-two Sources nFIQ nIRQ Embedded PeripheralEE Embedded Peripheral Embedded Peripheral APB Application Block Diagram Figure 44. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts) 131 6070A-ATARM-28-Oct-04 AIC Detailed Block Diagram Figure 45. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller External Source Input Stage Fast Interrupt Controller ARM Processor nFIQ nIRQ IRQ0-IRQn PIOIRQ Internal Source Input Stage Fast Forcing Interrupt Priority Controller Processor Clock Power Management Controller User Interface Wake Up Embedded Peripherals APB I/O Line Description Table 45. I/O Line Description Pin Name FIQ IRQ0 - IRQn Pin Description Fast Interrupt Interrupt 0 - Interrupt n Type Input Input Product Dependencies I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. Power Management Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and the Memory Controller. When a system interrupt 132 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 133 6070A-ATARM-28-Oct-04 Functional Description Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low levelsensitive modes, or in positive edge-triggered or negative edge-triggered modes. Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the "memorization" circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See "Priority Controller" on page 137.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See "Fast Forcing" on page 141.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see "Priority Controller" on page 137) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. Interrupt Clearing and Setting 134 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Internal Interrupt Source Input Stage Figure 46. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Source i Level/ Edge AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR Edge Detector Set Clear AIC_ISCR AIC_ICCR FF AIC_IDCR External Interrupt Source Input Stage Figure 47. External Interrupt Source Input Stage AIC_SMRi SRCTYPE Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Pos./Neg. Edge Detector Set AIC_ISCR AIC_ICCR Clear AIC_IDCR AIC_IECR High/Low FF 135 6070A-ATARM-28-Oct-04 Interrupt Latencies Global interrupt latencies depend on several parameters, including: * * * * The time the software masks the interrupts. Occurrence, either at the processor level or at the AIC level. The execution time of the instruction in progress when the interrupt occurs. The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. External Interrupt Edge Triggered Source Figure 48. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles External Interrupt Level Sensitive Source Figure 49. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 136 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Internal Interrupt Edge Triggered Source Figure 50. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active Internal Interrupt Level Sensitive Source Figure 51. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SVR (Source Vector Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 137 6070A-ATARM-28-Oct-04 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system's general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit "I" of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 138 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: - - - - - Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. Automatically clears the interrupt, if it has been programmed to be edge-triggered. Pushes the current level and the current interrupt number on to the stack. Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the "I" bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The "I" bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the "I" bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The "I" bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the Fast Interrupt Control 139 6070A-ATARM-28-Oct-04 fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: LDR PC, [PC, # -&F20] 3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is: 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR 140 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core. The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The Fast Interrupt Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. 141 6070A-ATARM-28-Oct-04 Figure 52. Fast Forcing Source 0 _ FIQ Input Stage AIC_IMR AIC_IPR Automatic Clear nFIQ Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n Input Stage Automatic Clear AIC_IMR AIC_IPR Priority Manager nIRQ Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n. Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: * * If an enabled interrupt with a higher priority than the current one is pending, it is stacked. If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. 142 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: * * An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. * The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 143 6070A-ATARM-28-Oct-04 Advanced Interrupt Controller (AIC) User Interface Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an 4-Kbyte offset. Table 46. Advanced Interrupt Controller (AIC) Register Mapping Offset 0000 0x04 --0x7C 0x80 0x84 --0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 Register Source Mode Register 0 Source Mode Register 1 --Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 --Source Vector Register 31 Interrupt Vector Register Fast Interrupt Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register Interrupt Disable Command Register Interrupt Clear Command Register Interrupt Set Command Register End of Interrupt Command Register Spurious Interrupt Vector Register Debug Control Register Reserved Fast Forcing Enable Register Fast Forcing Disable Register Fast Forcing Status Register Name AIC_SMR0 AIC_SMR1 --AIC_SMR31 AIC_SVR0 AIC_SVR1 --AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR ----AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR --AIC_FFER AIC_FFDR AIC_FFSR Access Read/Write Read/Write --Read/Write Read/Write Read/Write --Read/Write Read-only Read-only Read-only Read-only Read-only Read-only ----Write-only Write-only Write-only Write-only Write-only Read/Write Read/Write --Write-only Write-only Read-only Reset Value 0x0 0x0 --0x0 0x0 0x0 --0x0 0x0 0x0 0x0 0x0(1) 0x0 0x0 --------------0x0 0x0 ------0x0 Note: 1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 144 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Reset Value: 31 - 23 - 15 - 7 - Read/Write 0x0 30 - 22 - 14 - 6 SRCTYPE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PRIOR 24 - 16 - 8 - 0 * PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx. * SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. SRCTYPE 0 0 1 1 0 1 0 1 Internal Interrupt Sources Level Sensitive Edge Triggered Level Sensitive Edge Triggered 145 6070A-ATARM-28-Oct-04 AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Reset Value: 31 Read/Write 0x0 30 29 28 VECTOR 27 26 25 24 23 22 21 20 VECTOR 19 18 17 16 15 14 13 12 VECTOR 11 10 9 8 7 6 5 4 VECTOR 3 2 1 0 * VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. AIC Interrupt Vector Register Register Name: AIC_IVR Access Type: Reset Value: 31 Read-only 0 30 29 28 IRQV 27 26 25 24 23 22 21 20 IRQV 19 18 17 16 15 14 13 12 IRQV 11 10 9 8 7 6 5 4 IRQV 3 2 1 0 * IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 146 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Reset Value: 31 Read-only 0 30 29 28 FIQV 27 26 25 24 23 22 21 20 FIQV 19 18 17 16 15 14 13 12 FIQV 11 10 9 8 7 6 5 4 FIQV 3 2 1 0 * FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the Fast Interrupt Vector Register reads the value stored in AIC_SPU. 147 6070A-ATARM-28-Oct-04 AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-only 0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 IRQID 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. AIC Interrupt Pending Register Register Name: AIC_IPR Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending. 148 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Reset Value: 31 - 23 - 15 - 7 - Read-only 0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 NIRQ 24 - 16 - 8 - 0 NIFQ * NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. * NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 149 6070A-ATARM-28-Oct-04 AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID3: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 150 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ * FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 151 6070A-ATARM-28-Oct-04 AIC End of Interrupt Command Register Register Name: AIC_EOICR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 - The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Reset Value: 31 Read/Write 0 30 29 28 SIQV 27 26 25 24 23 22 21 20 SIQV 19 18 17 16 15 14 13 12 SIQV 11 10 9 8 7 6 5 4 SIQV 3 2 1 0 * SIQV: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 152 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary AIC Debug Control Register Register Name: AIC_DEBUG Access Type: Reset Value: 31 - 23 - 15 - 7 - Read/Write 0 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 GMSK 24 - 16 - 8 - 0 PROT * PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. * GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt. 153 6070A-ATARM-28-Oct-04 AIC Fast Forcing Disable Register Register Name: AIC_FFDR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt. AIC Fast Forcing Status Register Register Name: AIC_FFSR Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 Read-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 - * SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt. 154 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Clock Generator Description The Clock Generator is made up of 1 PLL, a Main Oscillator, an RC Oscillator and It provides the following clocks: * * * SLCK, the Slow Clock, which is the only permanent clock within the system. MAINCK is the output of the Main Oscillator PLLCK is the output of the Divider and PLL block The Clock Generator User Interface is embedded within the Power Management Controller one and is described in "Power Management Controller (PMC) User Interface" on page 166. However, the Clock Generator registers are named CKGR_. Slow Clock RC Oscillator The slow clock is the output of the RC Oscillator and is the only clock considered permanent in a system that includes the Power Management Controller. It is mandatory in the operations of the PMC. The user has to take the possible drifts of the RC Oscillator into account. More details are given in the DC Characteristics section of the product datasheet. Main Oscillator Figure 53 shows the Main Oscillator block diagram. Figure 53. Main Oscillator Block Diagram MOSCEN XIN XOUT Main Oscillator MAINCK Main Clock OSCOUNT SLCK Slow Clock Main Oscillator Counter Main Clock Frequency Counter MOSCS MAINF MAINRDY Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 54. The 1 k resistor is only required for crystals with frequencies lower than 8 MHz. The oscillator contains 25 pF capacitors on each XIN and XOUT pin. Consequently, CL1 and CL2 can be removed when a crystal with a load capacitance of 12.5 pF is used. For further details on the electrical characteristics of the Main Oscillator, see the DC Characteristics section of the product datasheet. 155 6070A-ATARM-28-Oct-04 Figure 54. Typical Crystal Connection XIN XOUT GND 1K CL1 CL2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off. When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor. Main Oscillator Control Main Clock Frequency Counter The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly. 156 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Divider and PLL Block The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 55 shows the block diagram of the divider and PLL block. Figure 55. Divider and PLL Block Diagram DIV MAINCK Divider MUL PLL OUT PLLCK PLLRC PLLCOUNT PLL Counter SLCK LOCK PLL Filter The PLL requires connection to an external second-order filter through the PLLRC pin. Figure 56 shows a schematic of these filters. Figure 56. PLL Capacitors and Resistors PLLRC PLL R C2 C1 GND Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0. The PLL allows multiplication of the divider's outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_PLLR are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. 157 6070A-ATARM-28-Oct-04 Power Management Controller (PMC) Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: * MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. Processor Clock (PCK), switched off when entering processor in idle mode. Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. UDP Clock (UDPCK), required by USB Device Port operations. Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins. * * * * Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL. The Master Clock Controller is made up of a clock selector and a prescaler. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a lower one to inform the software when the change is actually done. Figure 57. Master Clock Controller PMC_MCKR CSS PMC_MCKR PRES SLCK MAINCK PLLCK To the Processor Clock Controller (PCK) Master Clock Prescaler MCK Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). 158 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. USB Clock Controller The USB Source Clock is the PLL output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of 0.25% depending on the USBDIV bit in CKGR_PLLR. When the PLL output is stable, i.e., the LOCK bit is set: * The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit in PMC_SCSR gives the activity of this clock. The USB device port require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the Peripheral Clock Controller. Figure 58. USB Clock Controller USBDIV USB Source Clock Divider /1,/2,/4 UDP Clock (UDPCK) UDP Peripheral Clock Controller The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. Programmable Clock Output Controller The PMC controls 3 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). 159 6070A-ATARM-28-Oct-04 Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. Programming Sequence 1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register. Code Example: write_register(CKGR_MOR,0x00000701) Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles. So, the main oscillator will be enabled (MOSCS bit set) after 56 Slow Clock Cycles. 2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL and divider: All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register. The DIV field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned off. The OUT field is used to select the PLL B output frequency range. The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and 2047. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input frequency multiplied by (MUL + 1). The PLLCOUNT field specifies the number of slow clock cycles before LOCK bit is set in the PMC_SR register after CKGR_PLLR register has been written. Once the PMC_PLL register has been written, the user must wait for the LOCK bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCK has been enabled in the PMC_IER register. All parameters in CKGR_PLLR can be programmed in a single write operation. If at some stage one of the following parameters, MUL, DIV is modified, LOCK bit will go low to indicate that PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to wait for LOCK bit to be set before using the PLL output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s). 160 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Code Example: write_register(CKGR_PLLR,0x00040805) If PLL and divider are enabled, the PLL input clock is the main clock. PLL output clock is PLL input clock multiplied by 5. Once CKGR_PLLR has been written, LOCK bit will be set after eight slow clock cycles. 4. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to slow clock. Once PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. All parameters in PMC_MCKR can be programmed in a single write operation. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks. Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked again, LOCK goes high and MCKRDY is set. While PLL is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see "Clock Switching Waveforms" on page 163. Code Example: write_register(PMC_MCKR,0x00000011) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 3 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the Programmable clock divider source. Four clock options are available: main clock, slow clock, PLLCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is 161 6070A-ATARM-28-Oct-04 prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set. Code Example: write_register(PMC_PCK0,0x00000015) Programmable clock 0 is main clock divided by 32. 6. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 9 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled. Note: Each enabled peripheral clock corresponds to Master Clock. Code Examples: write_register(PMC_PCER,0x00000110) Peripheral clocks 4 and 8 are enabled. write_register(PMC_PCDR,0x00000010) Peripheral clock 4 is disabled. 162 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Clock Switching Details Master Clock Switching Timings Table 47 gives the worst case timing required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 47. Clock Switching Timings (Worst Case) From To Main Clock - SLCK PLL Clock 0.5 x Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock 4 x SLCK + 2.5 x Main Clock 3 x PLL Clock + 4 x SLCK + 1 x Main Clock 3 x PLL Clock + 5 x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK Main Clock SLCK PLL Clock - 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK Clock Switching Waveforms Figure 59. Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR 163 6070A-ATARM-28-Oct-04 Figure 60. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 61. Change PLL Programming Slow Clock PLL Clock LOCK MCKRDY Master Clock Slow Clock Write CKGR_PLLR 164 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 62. Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx PLL Clock is selected Write PMC_SCER PCKx is enabled Write PMC_SCDR PCKx is disabled 165 6070A-ATARM-28-Oct-04 Power Management Controller (PMC) User Interface Table 48. Power Management Controller (PMC) Register Mapping Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0038 0x003C 0x0040 0x0044 ... 0x0060 0x0064 0x0068 0x006C 0x0070 - 0x00FC Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register Reserved PLL Register Master Clock Register Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register ... Interrupt Enable Register Interrupt Disable Register Status Register Interrupt Mask Register Reserved Name PMC_SCER PMC_SCDR PMC _SCSR - PMC _PCER PMC_PCDR PMC_PCSR - CKGR_MOR CKGR_MCFR - CKGR_PLLR PMC_MCKR - - PMC_PCK0 PMC_PCK1 ... PMC_IER PMC_IDR PMC_SR PMC_IMR - ... Write-only Write-only Read-only Read-only - Access Write-only Write-only Read-only - Write-only Write-only Read-only - Read/Write Read-only - Read/Write Read/Write - - Read/Write Read/Write ... --0x18 0x0 - Reset Value - - 0x01 - - - 0x0 - 0x0 - 0x3F00 0x0 - - 0x0 0x0 166 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC System Clock Enable Register Register Name: PMC_SCER Access Type: 31 Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCK2 2 PCK1 1 PCK0 0 UDP - - - - - - PCK * PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor clock. * UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 167 6070A-ATARM-28-Oct-04 PMC System Clock Disable Register Register Name: PMC_SCDR Access Type: 31 Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCK2 2 PCK1 1 PCK0 0 UDP - - - - - - PCK * PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. * UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 168 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC System Clock Status Register Register Name: PMC_SCSR Access Type: 31 Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCK2 2 PCK1 1 PCK0 0 UDP - - - - - - PCK * PCK: Processor Clock Status 0 = The Processor clock is disabled.- 1 = The Processor clock is enabled. * UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled. * PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled. 169 6070A-ATARM-28-Oct-04 PMC Peripheral Clock Enable Register Register Name: PMC_PCER Access Type: 31 Write-only 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC. PMC Peripheral Clock Disable Register Register Name: PMC_PCDR Access Type: 31 Write-only 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. 170 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC Peripheral Clock Status Register Register Name: PMC_PCSR Access Type: 31 Read-only 30 29 28 27 26 25 24 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 - - * PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. PMC Clock Generator Main Oscillator Register Register Name: CKGR_MOR Access Type: Read/Write 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 OSCOUNT 7 - 6 - 5 - 4 - 3 - 2 - 1 OSCBYPASS 0 MOSCEN 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0. * OSCBYPASS: Oscillator Bypass 0 = No effect. 1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN. * OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time. 171 6070A-ATARM-28-Oct-04 PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFR Access Type: Read-only 31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MAINF 7 6 5 4 MAINF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 MAINRDY 8 * MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. * MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available. 172 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC Clock Generator PLL Register Register Name: CKGR_PLLR Access Type: Read/Write 31 - 23 30 - 22 29 USBDIV 21 20 MUL 15 OUT 7 6 5 4 DIV 3 14 13 12 11 PLLCOUNT 2 1 0 10 9 8 28 27 - 19 26 25 MUL 17 24 18 16 Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. * DIV: Divider DIV 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIV. * PLLCOUNT: PLL Counter Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written. * OUT: PLL Clock Frequency Range OUT 0 0 1 1 0 1 0 1 PLL Clock Frequency Range Refer to the DC Characteristics section of the product datasheet Reserved Refer to the DC Characteristics section of the product datasheet Reserved * MUL: PLL Multiplier 0 = The PLL is deactivated. 1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1. * USBDIV: Divider for USB Clock USBDIV 0 0 1 1 0 1 0 1 Divider for USB Clock(s) Divider output is PLL clock output. Divider output is PLL clock output divided by 2. Divider output is PLL clock output divided by 4. Reserved. 173 6070A-ATARM-28-Oct-04 PMC Master Clock Register Register Name: PMC_MCKR Access Type: 31 Read/Write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - PRES CSS * CSS: Master Clock Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected Reserved PLL Clock is selected. * PRES: Master Clock Prescaler PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved 174 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC Programmable Clock Register Register Name: PMC_PCKx Access Type: 31 Read/Write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - PRES CSS * CSS: Master Clock Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected Reserved PLL Clock is selected * PRES: Programmable Clock Prescaler PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved 175 6070A-ATARM-28-Oct-04 PMC Interrupt Enable Register Register Name: PMC_IER Access Type: 31 Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCKRDY2 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCK - MOSCS * MOSCS: Main Oscillator Status Interrupt Enable * LOCK: PLL Lock Interrupt Enable * MCKRDY: Master Clock Ready Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. PMC Interrupt Disable Register Register Name: PMC_IDR Access Type: 31 Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCKRDY2 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCK - MOSCS * MOSCS: Main Oscillator Status Interrupt Disable * LOCK: PLL Lock Interrupt Disable * MCKRDY: Master Clock Ready Interrupt Disable * PCKRDYx: Programmable Clock Ready x Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 176 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PMC Status Register Register Name: PMC_SR Access Type: 31 Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCKRDY2 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCK - MOSCS * MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. * LOCK: PLL Lock Status 0 = PLL is not locked 1 = PLL is locked. * MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready. * PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready. 177 6070A-ATARM-28-Oct-04 PMC Interrupt Mask Register Register Name: PMC_IMR Access Type: 31 Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 PCKRDY2 2 PCKRDY1 1 PCKRDY0 0 - - - - MCKRDY LOCK - MOSCS * MOSCS: Main Oscillator Status Interrupt Mask * LOCK: PLL Lock Interrupt Mask * MCKRDY: Master Clock Ready Interrupt Mask * PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled. 178 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit (DBGU) Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel's ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM. 179 6070A-ATARM-28-Oct-04 Block Diagram Figure 63. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral Data Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Baud Rate Generator Receive Parallel Input/ Output DRXD COMMRX ARM Processor nTRST COMMTX DCC Handler Chip ID ICE Access Handler Interrupt Control dbgu_irq ice_nreset force_ntrst Table 49. Debug Unit Pin Description Pin Name DRXD DTXD Description Debug Receive Data Debug Transmit Data Type Input Output Figure 64. Debug Unit Application Example Boot Program Debug Monitor Trace Manager Debug Unit RS232 Drivers Programming Tool Debug Console Trace Console 180 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Product Dependencies I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. Power Management Interrupt Source Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1. Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 63. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART. UART Operations Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). MCK Baud Rate = -------------------16 x CD Figure 65. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 181 6070A-ATARM-28-Oct-04 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 66. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 67. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. 182 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 68. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 69. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 70. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 71. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 183 6070A-ATARM-28-Oct-04 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 72. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. 184 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 73. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. 185 6070A-ATARM-28-Oct-04 Figure 74. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 186 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: * * * * * * EXT - shows the use of the extension identifier register NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size ARCH - identifies the set of embedded peripheral SRAMSIZ - indicates the size of the embedded SRAM EPROC - indicates the embedded ARM processor VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 187 6070A-ATARM-28-Oct-04 Debug Unit User Interface Table 50. Debug Unit Memory Map Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0X0040 0X0044 0X0048 0x004C - 0x00FC 0x0100 - 0x0124 Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR - DBGU_CIDR DBGU_EXID DBGU_FNR - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write - Read-only Read-only Read/Write - - Reset Value - 0x0 - - 0x0 - 0x0 - 0x0 - - - 0x0 - - 188 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Control Register Name: Access Type: 31 DBGU_CR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 RSTSTA 0 - 7 TXDIS - 6 TXEN - 5 RXDIS - 4 RXEN - 3 RSTTX - 2 RSTRX - 1 - - * RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. * RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. * RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. * RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. * TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. * TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. * RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 189 6070A-ATARM-28-Oct-04 Debug Unit Mode Register Name: Access Type: 31 DBGU_MR Read/Write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 CHMODE 7 - 14 - 13 - 12 - 11 - 10 PAR - 9 - 8 - 6 5 - 4 3 - 1 0 2 - - - - - - - - * PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity * CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 190 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Interrupt Enable Register Name: Access Type: 31 COMMRX 23 DBGU_IER Write-only 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Enable RXRDY Interrupt * TXRDY: Enable TXRDY Interrupt * ENDRX: Enable End of Receive Transfer Interrupt * ENDTX: Enable End of Transmit Interrupt * OVRE: Enable Overrun Error Interrupt * FRAME: Enable Framing Error Interrupt * PARE: Enable Parity Error Interrupt * TXEMPTY: Enable TXEMPTY Interrupt * TXBUFE: Enable Buffer Empty Interrupt * RXBUFF: Enable Buffer Full Interrupt * COMMTX: Enable COMMTX (from ARM) Interrupt * COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 191 6070A-ATARM-28-Oct-04 Debug Unit Interrupt Disable Register Name: Access Type: 31 COMMRX 23 DBGU_IDR Write-only 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Disable RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Disable End of Receive Transfer Interrupt * ENDTX: Disable End of Transmit Interrupt * OVRE: Disable Overrun Error Interrupt * FRAME: Disable Framing Error Interrupt * PARE: Disable Parity Error Interrupt * TXEMPTY: Disable TXEMPTY Interrupt * TXBUFE: Disable Buffer Empty Interrupt * RXBUFF: Disable Buffer Full Interrupt * COMMTX: Disable COMMTX (from ARM) Interrupt * COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 192 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Interrupt Mask Register Name: Access Type: 31 COMMRX 23 DBGU_IMR Read-only 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Mask RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Mask End of Receive Transfer Interrupt * ENDTX: Mask End of Transmit Interrupt * OVRE: Mask Overrun Error Interrupt * FRAME: Mask Framing Error Interrupt * PARE: Mask Parity Error Interrupt * TXEMPTY: Mask TXEMPTY Interrupt * TXBUFE: Mask TXBUFE Interrupt * RXBUFF: Mask RXBUFF Interrupt * COMMTX: Mask COMMTX Interrupt * COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 193 6070A-ATARM-28-Oct-04 Debug Unit Status Register Name: Access Type: 31 COMMRX 23 DBGU_SR Read-only 30 COMMTX 22 29 28 27 26 25 24 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 4 ENDTX - 11 TXBUFE 3 ENDRX - 10 - 9 TXEMPTY 1 TXRDY - 8 - 7 PARE - 6 FRAME - 5 OVRE - 2 - 0 RXRDY - * RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. * TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. * ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. * ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. * OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. * PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. * TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. * TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. * RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. 194 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. * COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 195 6070A-ATARM-28-Oct-04 Debug Unit Receiver Holding Register Name: Access Type: 31 DBGU_RHR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 RXCHR - 3 - 2 - 1 - 0 * RXCHR: Received Character Last received character if RXRDY is set. 196 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Transmit Holding Register Name: Access Type: 31 DBGU_THR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 TXCHR - 3 - 2 - 1 - 0 * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. Debug Unit Baud Rate Generator Register Name: Access Type: 31 DBGU_BRGR Read/Write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 CD - 11 - 10 - 9 - 8 7 6 5 4 CD 3 2 1 0 * CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 197 6070A-ATARM-28-Oct-04 Debug Unit Chip ID Register Name: Access Type: 31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 DBGU_CIDR Read-only 30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 * VERSION: Version of the Device * EPROC: Embedded Processor EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS * NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved 198 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * NVPSIZ2: Second Nonvolatile Program Memory Size NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved * SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes Reserved Reserved 4K bytes Reserved 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes 199 6070A-ATARM-28-Oct-04 * ARCH: Architecture Identifier ARCH Hex 0x40 0x63 0x55 0x42 0x92 0x34 0x70 0x71 0x72 0x73 0x19 Bin 0100 0000 0110 0011 0101 0101 0100 0010 1001 0010 0011 0100 0111 0000 0111 0001 0111 0010 0111 0011 0001 1001 Architecture AT91x40 Series AT91x63 Series AT91x55 Series AT91x42 Series AT91x92 Series AT91x34 Series AT91SAM7Sxx and AT91SAM7Axx Series AT91SAM7Xxx Series AT91SAM7Exx Series AT91SAM7Lxx Series AT91SAM9xx Series * NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size * EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 200 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Chip ID Extension Register Name: Access Type: 31 DBGU_EXID Read-only 30 29 28 EXID 27 26 25 24 23 22 21 20 EXID 19 18 17 16 15 14 13 12 EXID 11 10 9 8 7 6 5 4 EXID 3 2 1 0 * EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. Debug Unit Force NTRST Register Name: Access Type: 31 DBGU_FNR Read/Write 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 FNTRST - - - - - - - * FNTRST: Force NTRST 0 = NTRST of the ARM processor's TAP controller is driven by the ice_nreset signal. 1 = NTRST of the ARM processor's TAP controller is held low. 201 6070A-ATARM-28-Oct-04 202 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Parallel Input/Output Controller (PIO) Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: * * * * * An input change interrupt enabling level change detection on any I/O line. A glitch filter providing rejection of pulses lower than one-half of clock cycle. Multi-drive capability similar to an open drain I/O line. Control of the the pull-up of the I/O line. Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 203 6070A-ATARM-28-Oct-04 Block Diagram Figure 75. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Data, Enable Embedded Peripheral Up to 32 peripheral IOs PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Application Block Diagram Figure 76. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 204 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. Power Management Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 205 6070A-ATARM-28-Oct-04 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 77. In this description each signal shown represents but one of up to 32 possible indexes. Figure 77. I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_ODR[0] 1 PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0] Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output 0 0 0 1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0 0 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 1 1 1 PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0] Pad 0 Peripheral A Input Peripheral B Input PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1 PIO_ISR[0] (Up to 32 possible inputs) PIO Interrupt PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] Pull-up Resistor Control 206 Each I/O line is designed with an embedded pull-up resistor. The value of this resistor is about 100 k (see the product electrical characteristics for more details about this value). The pull- AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_PDR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on 207 6070A-ATARM-28-Oct-04 the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multidriver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. Output Line Timings Figure 78 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 78 also shows when the feedback in PIO_PDSR is available. Figure 78. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 cycles PIO_PDSR 2 cycles Inputs The level on each I/O line can be read through PIO_PDSR (Peripheral Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. 208 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 79. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. Figure 79. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. 209 6070A-ATARM-28-Oct-04 Figure 80. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 210 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary I/O Lines Programming Example The programing example as shown in Table 51 below is used to define the following configuration. * * * * * * * 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), opendrain, with pull-up resistor Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pullup resistors, glitch filters and input change interrupts Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 51. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 211 6070A-ATARM-28-Oct-04 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 52. Parallel Input/Output Controller (PIO) Register Mapping Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register PIO Enable Register PIO Disable Register PIO Status Register (1) Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register(2) Pin Data Status Register(3) Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register(4) Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only - - 0x00000000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only - - 0x00000000 0x00000000 - - 0x00000000 - - 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only - - 0x0000 0000 PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only - - 0x0000 0000 Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset Value - - 0x0000 0000 212 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 52. Parallel Input/Output Controller (PIO) Register Mapping (Continued) Offset 0x0070 0x0074 0x0078 0x007C - 0x009C 0x00A0 0x00A4 0x00A8 0x00AC - 0x00FC Notes: 1. 2. 3. 4. Register Peripheral A Select Register(5) Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only - - 0x00000000 (5) (5) Name PIO_ASR PIO_BSR PIO_ABSR Access Write-only Write-only Read-only Reset Value - - 0x00000000 Reset value of PIO_PSR depends on the product implementation. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. Reset value of PIO_PDSR depends on the level of the I/O lines. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 213 6070A-ATARM-28-Oct-04 PIO Controller PIO Enable Register Name: Access Type: 31 PIO_PER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). PIO Controller PIO Disable Register Name: Access Type: 31 PIO_PDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 214 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Controller PIO Status Register Name: Access Type: 31 PIO_PSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). PIO Controller Output Enable Register Name: Access Type: 31 PIO_OER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 215 6070A-ATARM-28-Oct-04 PIO Controller Output Disable Register Name: Access Type: 31 PIO_ODR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. PIO Controller Output Status Register Name: Access Type: 31 PIO_OSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 216 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Controller Input Filter Enable Register Name: Access Type: 31 PIO_IFER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. PIO Controller Input Filter Disable Register Name: Access Type: 31 PIO_IFDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 217 6070A-ATARM-28-Oct-04 PIO Controller Input Filter Status Register Name: Access Type: 31 PIO_IFSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. PIO Controller Set Output Data Register Name: Access Type: 31 PIO_SODR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 218 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Controller Clear Output Data Register Name: Access Type: 31 PIO_CODR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. PIO Controller Output Data Status Register Name: Access Type: 31 PIO_ODSR Read-only or Read/Write 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 219 6070A-ATARM-28-Oct-04 PIO Controller Pin Data Status Register Name: Access Type: 31 PIO_PDSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. PIO Controller Interrupt Enable Register Name: Access Type: 31 PIO_IER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 220 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Controller Interrupt Disable Register Name: Access Type: 31 PIO_IDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. PIO Controller Interrupt Mask Register Name: Access Type: 31 PIO_IMR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 221 6070A-ATARM-28-Oct-04 PIO Controller Interrupt Status Register Name: Access Type: 31 PIO_ISR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. PIO Multi-driver Enable Register Name: Access Type: 31 PIO_MDER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 222 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Multi-driver Disable Register Name: Access Type: 31 PIO_MDDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. PIO Multi-driver Status Register Name: Access Type: 31 PIO_MDSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 223 6070A-ATARM-28-Oct-04 PIO Pull Up Disable Register Name: Access Type: 31 PIO_PUDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. PIO Pull Up Enable Register Name: Access Type: 31 PIO_PUER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 224 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Pull Up Status Register Name: Access Type: 31 PIO_PUSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. PIO Peripheral A Select Register Name: Access Type: 31 PIO_ASR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 225 6070A-ATARM-28-Oct-04 PIO Peripheral B Select Register Name: Access Type: 31 PIO_BSR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. PIO Peripheral A B Status Register Name: Access Type: 31 PIO_ABSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 226 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PIO Output Write Enable Register Name: Access Type: 31 PIO_OWER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. PIO Output Write Disable Register Name: Access Type: 31 PIO_OWDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 227 6070A-ATARM-28-Oct-04 PIO Output Write Status Register Name: Access Type: 31 PIO_OWSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 * P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 228 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Serial Peripheral Interface (SPI) Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: * * Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. * * 229 6070A-ATARM-28-Oct-04 Block Diagram Figure 81. Block Diagram PDC APB SPCK MISO MCK SPI Interface DIV PIO MOSI NPCS0/NSS NPCS1 NPCS2 MCK(1) N Interrupt Control NPCS3 PMC SPI Interrupt Note: 1. N = 32 Application Block Diagram Figure 82. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 230 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Signal Description Table 53. Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Power Management Interrupt The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. 231 6070A-ATARM-28-Oct-04 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 54 shows the four modes and corresponding parameter settings. Table 54. SPI Bus Protocol Mode SPI Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 1 0 1 0 Figure 83 and Figure 84 show examples of data transfers. 232 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 83. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 84. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 233 6070A-ATARM-28-Oct-04 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. No transfer is started when writing into the SPI_TDR if the PCS field does not select a slave. The PCS field is set by writing the SPI_TDR in variable mode, or the SPI_MR in fixed mode, depending on the value of PCS field. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, no data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 85 on page 235 shows a block diagram of the SPI when operating in Master Mode. Figure 86 on page 236 shows a flow chart describing how transfers are handled. 234 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Master Mode Block Diagram Figure 85. Master Mode Block Diagram FDIV MCK SPI_CSR0..3 SCBR 0 Baud Rate Generator SPCK MCK/N 1 SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB SPI_RDR RD RDRF OVRES MISO Shift Register MSB MOSI SPI_TDR TD SPI_CSR0..3 CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral SPI_RDR PCS NPCS3 NPCS2 NPCS1 TDRE MSTR NPCS0 MODFDIS MODF 235 6070A-ATARM-28-Oct-04 Master Mode Flow Diagram Figure 86. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral 1 SPI_TDR(PCS) = NPCS ? no NPCS = 0xF SPI_MR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = SPI_TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 236 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 2 and 255. The selection between Master Clock or Master Clock divided by N is done by the FDIV value set in the Mode Register This allows a maximum operating baud rate at up to Master Clock/2 and a minimum operating baud rate of MCK divided by 255*32. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. Transfer Delays Figure 87 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: * The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select * * These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 87. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: * * Fixed Peripheral Select: SPI exchanges data with only one peripheral Variable Peripheral Select: Data can be exchanged with more than one peripheral 237 6070A-ATARM-28-Oct-04 Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS fields of the Chip Select Registers have no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 88 shows different peripheral deselection cases and the effect of the CSAAT bit. 238 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 88. Peripheral Deselection CSAAT = 0 CSAAT = 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write SPI_TDR Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. As this pin is generally configured in open-drain, it is important that a pull up resistor is connected on the NPCS0 line, so that a high level is guaranteed and no spurious mode fault is detected. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. 239 6070A-ATARM-28-Oct-04 The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to SPI_RDR is aborted. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 89 shows a block diagram of the SPI when operating in Slave Mode. Figure 89. Slave Mode Functional Block Diagram SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock Shift Register MSB MISO SPI_TDR FLOAD TD TDRE 240 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Serial Peripheral Interface (SPI) User Interface Table 55. Serial Peripheral Interface (SPI) Register Mapping Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00FC 0x100 - 0x124 Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 - Read/Write Read/Write Read/Write Read/Write - 0x0 0x0 0x0 0x0 - Register Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 241 6070A-ATARM-28-Oct-04 SPI Control Register Name: Access Type: 31 SPI_CR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 LASTXFER 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SWRST - - - - - SPIDIS SPIEN * SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. * SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. * SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 242 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SPI Mode Register Name: Access Type: 31 SPI_MR Read/Write 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 LLB - - MODFDIS FDIV PCSDEC PS MSTR * MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. * PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. * PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15. * FDIV: Clock Selection 0 = The SPI operates at MCK. 1 = The SPI operates at MCK/N. * MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. * LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. 243 6070A-ATARM-28-Oct-04 * PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods (or 6*N MCK periods if FDIV is set) will be inserted by default. Otherwise, the following equation determines the delay: If FDIV is 0: DLYBCS Delay Between Chip Selects = ---------------------MCK If FDIV is 1: DLYBCS x N Delay Between Chip Selects = -------------------------------MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 244 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SPI Receive Data Register Name: Access Type: 31 SPI_RDR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD * RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. * PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 245 6070A-ATARM-28-Oct-04 SPI Transmit Data Register Name: Access Type: 31 SPI_TDR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 LASTXFER 16 - 15 - 14 - 13 - 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD * TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 246 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SPI Status Register Name: Access Type: 31 SPI_SR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 SPIENS 8 - 7 - 6 - 5 - 4 - 3 - 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. * TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. * OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. * ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR or SPI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR or SPI_RNCR. * ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR or SPI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR or SPI_TNCR. * RXBUFF: RX Buffer Full 0 = SPI_RCR or SPI_RNCR has a value other than 0. 1 = Both SPI_RCR and SPI_RNCR has a value of 0. * TXBUFE: TX Buffer Empty 0 = SPI_TCR or SPI_TNCR has a value other than 0. 1 = Both SPI_TCR and SPI_TNCR has a value of 0. * NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. 247 6070A-ATARM-28-Oct-04 * TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. * SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. 248 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SPI Interrupt Enable Register Name: Access Type: 31 SPI_IER Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Enable * TDRE: SPI Transmit Data Register Empty Interrupt Enable * MODF: Mode Fault Error Interrupt Enable * OVRES: Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * TXEMPTY: Transmission Registers Empty Enable * NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 249 6070A-ATARM-28-Oct-04 SPI Interrupt Disable Register Name: Access Type: 31 SPI_IDR Write-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Disable * TDRE: SPI Transmit Data Register Empty Interrupt Disable * MODF: Mode Fault Error Interrupt Disable * OVRES: Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * TXEMPTY: Transmission Registers Empty Disable * NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 250 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SPI Interrupt Mask Register Name: Access Type: 31 SPI_IMR Read-only 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF * RDRF: Receive Data Register Full Interrupt Mask * TDRE: SPI Transmit Data Register Empty Interrupt Mask * MODF: Mode Fault Error Interrupt Mask * OVRES: Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * TXEMPTY: Transmission Registers Empty Mask * NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 251 6070A-ATARM-28-Oct-04 SPI Chip Select Register Name: Access Type: 31 SPI_CSR0... SPI_CSR3 Read/Write 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS CSAAT - NCPHA CPOL * CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. * NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 252 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: If FDIV is 0: MCK SPCK Baudrate = -------------SCBR If FDIV is 1: MCK SPCK Baudrate = ----------------------------( N x SCBR ) Note: N = 32 Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: If FDIV is 0: DLYBS Delay Before SPCK = -----------------MCK If FDIV is 1: N x DLYBS Delay Before SPCK = ---------------------------MCK Note: N = 32 * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: If FDIV is 0: 32 x DLYBCT SCBR Delay Between Consecutive Transfers = ----------------------------------- + ---------------MCK 2MCK If FDIV is 1: 32 x N x DLYBCT N x SCBR Delay Between Consecutive Transfers = ---------------------------------------------- + -----------------------2MCK MCK Note: N = 32 253 6070A-ATARM-28-Oct-04 254 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Two-wire Interface (TWI) Overview The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byteoriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Figure 90. Block Diagram APB Bridge Block Diagram TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC Application Block Diagram Figure 91. Application Block Diagram VDD R TWD TWCK R Host with TWI Interface AT24LC16 U1 Slave 1 AT24LC16 U2 Slave 2 LCD Controller U3 Slave 3 255 6070A-ATARM-28-Oct-04 Product Dependencies I/O Lines Description Table 56. I/O Lines Description Pin Name TWD TWCK Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 91 on page 255). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: * Program the PIO controller to: - - Dedicate TWD and TWCK as peripheral lines. Define TWD and TWCK as open-drain. Power Management * Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. Interrupt 256 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 93 on page 257). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 92 on page 257). * * A high-to-low transition on the TWD line while TWCK is high defines the START condition. A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 92. START and STOP Conditions TWD TWCK Start Stop Figure 93. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop Modes of Operation The TWI has two modes of operation: * * Master transmitter mode Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks. Transmitting Data After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in 257 6070A-ATARM-28-Oct-04 the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 95 below). The master generates a stop condition to end the transfer. The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address). The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). Figure 94. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 95. Master Write with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A DATA A DATA A DATA A P TXCOMP Write THR TXRDY Write THR Write THR Write THR Figure 96. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P 258 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 97. Master Read with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P TXCOMP Write START Bit RXRDY Write STOP Bit Read RHR Read RHR * * * * * * S = Start P = Stop W = Write/Read A = Acknowledge DADR= Device Address IADR = Internal Address Figure 98 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 98. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 259 6070A-ATARM-28-Oct-04 Read/Write Flowcharts The following flowcharts shown in Figure 99 on page 260 and in Figure 100 on page 261 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 99. TWI Write in Master Mode START Set TWI clock: TWI_CWGR = clock Set the control register: - Master enable TWI_CR = MSEN Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Set theinternal address TWI_IADR = address Yes Load transmit register TWI_THR = Data to send Start the transfer TWI_CR = START Read status register TWI_THR = data to send TXRDY = 0? Yes Data to send? Yes Stop the transfer TWI_CR = STOP Read status register TXCOMP = 0? Yes END 260 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 100. TWI Read in Master Mode START Set TWI clock: TWI_CWGR = clock Set the control register: - Master enable - Slave disable TWI_CR = MSEN Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Read ==> bit MREAD = 0 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read status register RXRDY = 0? Yes Data to read? Yes Stop the transfer TWI_CR = STOP Read status register TXCOMP = 0? Yes END 261 6070A-ATARM-28-Oct-04 Two-wire Interface (TWI) User Interface Table 57. Two-wire Interface (TWI) Register Mapping Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038-0x00FC Register Control Register Master Mode Register Reserved Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR - TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR - Access Write-only Read/Write - Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Read/Write - Reset Value N/A 0x0000 - 0x0000 0x0000 0x0008 N/A N/A 0x0000 0x0000 0x0000 - 262 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TWI Control Register Register Name: Access Type: 31 - 23 - 15 - 7 SWRST TWI_CR Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 MSDIS 26 - 18 - 10 - 2 MSEN 25 - 17 - 9 - 1 STOP 24 - 16 - 8 - 0 START * START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. * STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. * MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled. * MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. * SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 263 6070A-ATARM-28-Oct-04 TWI Master Mode Register Register Name: Address Type: 31 - 23 - 15 - 7 - TWI_MMR Read/Write 30 - 22 29 - 21 28 - 20 27 - 19 DADR 11 - 3 - 26 - 18 25 - 17 24 - 16 14 - 6 - 13 - 5 - 12 MREAD 4 - 10 - 2 - 9 IADRSZ 1 - 8 0 - * IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address * MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. * DADR: Device Address The device address is used in Master Mode to access slave devices in read or write mode. 264 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TWI Internal Address Register Register Name: Access Type: 31 - 23 TWI_IADR Read/Write 30 - 22 29 - 21 28 - 20 IADR 27 - 19 26 - 18 25 - 17 24 - 16 15 14 13 12 IADR 11 10 9 8 7 6 5 4 IADR 3 2 1 0 * IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. TWI Clock Waveform Generator Register Register Name: Access Type: 31 - 23 - 15 TWI_CWGR Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CHDIV 27 - 19 - 11 26 - 18 25 - 17 CKDIV 9 24 - 16 10 8 7 6 5 4 CLDIV 3 2 1 0 * CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV x 2 CKDIV ) + 3 ) x T MCK * CHDIV: Clock High Divider The SCL high period is defined as follows: T hi gh = ( ( CHDIV x 2 CKDIV ) + 3 ) x T MCK * CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 265 6070A-ATARM-28-Oct-04 TWI Status Register Register Name: Access Type: 31 - 23 - 15 - 7 UNRE TWI_SR Read-only 30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received. 1 = When both holding and shift registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI). * RXRDY: Receive Holding Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. * TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). * OVRE: Overrun Error 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. * UNRE: Underrun Error 0 = No underrun error 1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set. * NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read. 266 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TWI Interrupt Enable Register Register Name: Access Type: 31 - 23 - 15 - 7 UNRE TWI_IER Write-only 30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt. 267 6070A-ATARM-28-Oct-04 TWI Interrupt Disable Register Register Name: Access Type: 31 - 23 - 15 - 7 UNRE TWI_IDR Write-only 30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt. 268 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TWI Interrupt Mask Register Register Name: Access Type: 31 - 23 - 15 - 7 UNRE TWI_IMR Read-only 30 - 22 - 14 - 6 OVRE 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP * TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * OVRE: Overrun Error * UNRE: Underrun Error * NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 269 6070A-ATARM-28-Oct-04 TWI Receive Holding Register Register Name: Access Type: 31 - 23 - 15 - 7 TWI_RHR Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * RXDATA: Master or Slave Receive Holding Data TWI Transmit Holding Register Register Name: Access Type: 31 - 23 - 15 - 7 TWI_THR Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * TXDATA: Master or Slave Transmit Holding Data 270 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Universal Synchronous/Asynchronous Receiver/Transmitter (USART) Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multi-drop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral Data Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 271 6070A-ATARM-28-Oct-04 Block Diagram Figure 101. USART Block Diagram Peripheral Data Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 272 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Application Block Diagram Figure 102. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus I/O Lines Description Table 58. I/O Line Description Name SCK TXD RXD RI DSR DCD DTR CTS RTS Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level 273 6070A-ATARM-28-Oct-04 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. All the pins of the modems may or may not not be implemented on the USART within a product. Frequently, only the USART1 is fully equipped with all the modem signals. For the other USARTs of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 274 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: * 5- to 9-bit full-duplex asynchronous serial communication - - - - - - - - * - - - - - - - - * * * * MSB- or LSB-first 1, 1.5 or 2 stop bits Parity even, odd, marked, space or none By 8 or by 16 over-sampling receiver frequency Optional hardware handshaking Optional modem signals management Optional break management Optional multi-drop serial communication MSB- or LSB-first 1 or 2 stop bits Parity even, odd, marked, space or none By 8 or by 16 over-sampling frequency Optional Hardware handshaking Optional Modem signals management Optional Break management Optional Multi-Drop serial communication High-speed 5- to 9-bit full-duplex synchronous serial communication RS485 with driver control signal ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit InfraRed IrDA Modulation and Demodulation Test modes - Remote loopback, local loopback, automatic echo Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: * * * the Master Clock MCK a division of the Master Clock, the divider being product dependent, but generally set to 8 the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. 275 6070A-ATARM-28-Oct-04 Figure 103. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 - Over )CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. Baud Rate Calculation Example Table 59 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 59. Baud Rate Example (OVER = 0) Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 6 8 8 12 13 20 20 23 24 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% Error 276 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 59. Baud Rate Example (OVER = 0) (Continued) Source Clock 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000 Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 CD 30 39 40 40 52 53 54 65 81 98 114 Actual Baud Rate 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 Error 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06% The baud rate is calculated with the following formula: BaudRate = MCK CD x 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 - -------------------------------------------------ActualBaudRate Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. SelectedClock BaudRate = ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- x f Fi where: * * * * B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) 6070A-ATARM-28-Oct-04 277 Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 60. Table 60. Binary and Decimal Values for D DI field Di (decimal) 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 61. Table 61. Binary and Decimal Values for F FI field Fi (decimal 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 62 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 62. Possible Values for the Fi/Di Ratio Fi/Di 1 2 4 8 16 32 12 20 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 104 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. 278 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 104. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. 279 6070A-ATARM-28-Oct-04 Figure 105. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. Figure 106. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. 280 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 107 and Figure 108 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 107. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 108. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 281 6070A-ATARM-28-Oct-04 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 109 illustrates a character reception in synchronous mode. Figure 109. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 110. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 282 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, which is discussed in a separate paragraph. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the odd parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0.If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 63 shows an example of the parity bit for the character 0x41 (character ASCII "A") depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. I Table 63. Parity Bit Examples Character A A A A A Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 111 illustrates the parity bit status setting and clearing. Figure 111. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 283 6070A-ATARM-28-Oct-04 Multi-drop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x7, the USART runs in Multi-drop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multi-drop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 112, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. Figure 112. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY 284 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 64 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 64. Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 Bit time s 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. The user can either: * Obtain an interrupt when a time-out is detected after having received at least one character. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. Obtain a periodic interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. * If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 113 shows the block diagram of the Receiver Time-out feature. 285 6070A-ATARM-28-Oct-04 Figure 113. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 65 gives the maximum time-out period for some standard baud rates.t Table 65. Maximum Time-out Period Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 56000 57600 200000 Bit Time s 1 667 833 417 208 104 69 52 35 30 18 17 5 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 1 170 1 138 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. 286 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 114. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 115 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STP BRK) commands on the TXD line. 287 6070A-ATARM-28-Oct-04 Figure 115. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmuission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 116. Figure 116. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 117 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. 288 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 117. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 118 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 118. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see "Baud Rate Generator" on page 275). The USART connects to a smart card as shown in Figure 119. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 119. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. 289 6070A-ATARM-28-Oct-04 The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 120. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 121. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 120. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 121. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Receive NACK Inhibit 290 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the chara cte r b efore moving on to the n ext o ne. Rep etition is enab led by writin g th e MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 122. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 122. Connection to IrDA Transceivers Protocol T = 1 IrDA Mode USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 291 6070A-ATARM-28-Oct-04 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 66. Table 66. IrDA Pulse Duration Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 s 19.53 s 9.77 s 4.88 s 3.26 s 1.63 s Figure 123 shows an example of character transmission. Figure 123. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Start Bit 1 TXD Bit Period 3 16 Bit Period IrDA Baud Rate Table 67 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of 1.87% must be met. Table 67. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 53 65 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% 0.63% 0.16% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 4.88 4.88 292 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 67. IrDA Baud Rate Error (Continued) Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 124 illustrates the operations of the IrDA demodulator. Figure 124. IrDA Demodulator Operations MCK RXD Counter Value 6 5 4 3 2 6 6 5 4 3 2 1 0 Pulse Accepted Receiver Input Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 293 6070A-ATARM-28-Oct-04 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 125. Figure 125. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 126 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 126. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 294 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 68 gives the correspondence of the USART signals with modem connection standards. Table 68. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the RTS and DTR output pins is performed by witting the Control Register (US_CR) with the RTSDIS, RTSEN, DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable commands force the corresponding pin to its active level, i.e. low. The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 295 6070A-ATARM-28-Oct-04 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 127. Normal Mode Configuration RXD Receiver Normal Mode TXD Transmitter Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 128. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 128. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 129. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 129. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 130. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. 296 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 130. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 297 6070A-ATARM-28-Oct-04 USART User Interface Table 69. USART Register Mapping Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C - 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 - 0x00FC 0x0100 - 0x0128 Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_FIDI US_NER - US_IF - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write - Read/Write Read-only - Read/Write - - Reset State - - - - 0 - 0 - 0 0 0 - 0x174 - - 0 - - 298 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Control Register Name: Access Type: 31 - 23 - 15 RETTO 7 TXDIS US_CR Write-only 30 - 22 - 14 RSTNACK 6 TXEN 29 - 21 - 13 RSTIT 5 RXDIS 28 - 20 - 12 SENDA 4 RXEN 27 - 19 RTSDIS 11 STTTO 3 RSTTX 26 - 18 RTSEN 10 STPBRK 2 RSTRX 25 - 17 DTRDIS 9 STTBRK 1 - 24 - 16 DTREN 8 RSTSTA 0 - * RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. * RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. * RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. * RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. * TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. * TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. * RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. * STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. * STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. 299 6070A-ATARM-28-Oct-04 * STTTO: Start Time-out 0: No effect 1: Starts waiting for a character before clocking the time-out counter. * SENDA: Send Address 0: No effect. 1: In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. * RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. * RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. * RETTO: Rearm Time-out 0: No effect 1: Restart Time-out * DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. * DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. * RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. * RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 300 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Mode Register Name: Access Type: 31 - 23 - 15 CHMODE 7 CHRL 6 5 USCLKS US_MR Read/Write 30 - 22 - 14 29 - 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 - 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE * USART_MODE USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved * USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK / DIV Reserved SCK * CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits 301 6070A-ATARM-28-Oct-04 * SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. * PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multi-drop mode * NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved * CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. * MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. * MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. * CKLO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. * OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. 302 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. * DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. * MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. * FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 303 6070A-ATARM-28-Oct-04 USART Interrupt Enable Register Name: Access Type: 31 - 23 - 15 - 7 PARE US_IER Write-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY * RXRDY: RXRDY Interrupt Enable * TXRDY: TXRDY Interrupt Enable * RXBRK: Receiver Break Interrupt Enable * ENDRX: End of Receive Transfer Interrupt Enable * ENDTX: End of Transmit Interrupt Enable * OVRE: Overrun Error Interrupt Enable * FRAME: Framing Error Interrupt Enable * PARE: Parity Error Interrupt Enable * TIMEOUT: Time-out Interrupt Enable * TXEMPTY: TXEMPTY Interrupt Enable * ITERATION: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Enable * RXBUFF: Buffer Full Interrupt Enable * NACK: Non Acknowledge Interrupt Enable * RIIC: Ring Indicator Input Change Enable * DSRIC: Data Set Ready Input Change Enable * DCDIC: Data Carrier Detect Input Change Interrupt Enable * CTSIC: Clear to Send Input Change Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. 304 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Interrupt Disable Register Name: Access Type: 31 - 23 - 15 - 7 PARE US_IDR Write-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY * RXRDY: RXRDY Interrupt Disable * TXRDY: TXRDY Interrupt Disable * RXBRK: Receiver Break Interrupt Disable * ENDRX: End of Receive Transfer Interrupt Disable * ENDTX: End of Transmit Interrupt Disable * OVRE: Overrun Error Interrupt Disable * FRAME: Framing Error Interrupt Disable * PARE: Parity Error Interrupt Disable * TIMEOUT: Time-out Interrupt Disable * TXEMPTY: TXEMPTY Interrupt Disable * ITERATION: Iteration Interrupt Disable * TXBUFE: Buffer Empty Interrupt Disable * RXBUFF: Buffer Full Interrupt Disable * NACK: Non Acknowledge Interrupt Disable * RIIC: Ring Indicator Input Change Disable * DSRIC: Data Set Ready Input Change Disable * DCDIC: Data Carrier Detect Input Change Interrupt Disable * CTSIC: Clear to Send Input Change Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. 305 6070A-ATARM-28-Oct-04 USART Interrupt Mask Register Name: Access Type: 31 - 23 - 15 - 7 PARE US_IMR Read-only 30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY * RXRDY: RXRDY Interrupt Mask * TXRDY: TXRDY Interrupt Mask * RXBRK: Receiver Break Interrupt Mask * ENDRX: End of Receive Transfer Interrupt Mask * ENDTX: End of Transmit Interrupt Mask * OVRE: Overrun Error Interrupt Mask * FRAME: Framing Error Interrupt Mask * PARE: Parity Error Interrupt Mask * TIMEOUT: Time-out Interrupt Mask * TXEMPTY: TXEMPTY Interrupt Mask * ITERATION: Iteration Interrupt Mask * TXBUFE: Buffer Empty Interrupt Mask * RXBUFF: Buffer Full Interrupt Mask * NACK: Non Acknowledge Interrupt Mask * RIIC: Ring Indicator Input Change Mask * DSRIC: Data Set Ready Input Change Mask * DCDIC: Data Carrier Detect Input Change Interrupt Mask * CTSIC: Clear to Send Input Change Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. 306 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Channel Status Register Name: Access Type: 31 - 23 CTS 15 - 7 PARE US_CSR Read-only 30 - 22 DCD 14 - 6 FRAME 29 - 21 DSR 13 NACK 5 OVRE 28 - 20 RI 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 DCDIC 10 ITERATION 2 RXBRK 25 - 17 DSRIC 9 TXEMPTY 1 TXRDY 24 - 16 RIIC 8 TIMEOUT 0 RXRDY * RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. * TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. * RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. * ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. * ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. * OVRE: Overrun Error 0: No overrun error has occurred since since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. * PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. * TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command. 307 6070A-ATARM-28-Oct-04 * TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There is at least one character in either US_THR or the Transmit Shift Register. * ITERATION: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSIT. 1: Maximum number of repetitions has been reached since the last RSIT. * TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. * RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. * NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. * RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. * DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. * DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. * CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. * RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. * DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. * DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. * CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. 308 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Receive Holding Register Name: Access Type: 31 - 23 - 15 - 7 US_RHR Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 RXCHR 0 * RXCHR: Received Character Last character received if RXRDY is set. USART Transmit Holding Register Name: Access Type: 31 - 23 - 15 - 7 US_THR Write-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 TXCHR 0 * TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 309 6070A-ATARM-28-Oct-04 USART Baud Rate Generator Register Name: Access Type: 31 - 23 - 15 US_BRGR Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CD 7 6 5 4 CD 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * CD: Clock Divider USART_MODE CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO ISO7816 SYNC = 1 USART_MODE = ISO7816 310 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART Receiver Time-out Register Name: Access Type: 31 US_RTOR Read/Write 30 29 28 27 26 25 24 - 23 - 15 - 22 - 14 - 21 - 13 - 20 - 12 TO - 19 - 11 - 18 - 10 - 17 - 9 - 16 - 8 7 6 5 4 TO 3 2 1 0 * TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 311 6070A-ATARM-28-Oct-04 USART Transmitter Timeguard Register Name: Access Type: 31 - 23 - 15 - 7 US_TTGR Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TG 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 312 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USART FI DI RATIO Register Name: Access Type: Reset Value: 31 - 23 - 15 - 7 US_FIDI Read/Write 0x174 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FI_DI_RATIO 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FI_DI_RATIO 1 24 - 16 - 8 2 0 * FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 313 6070A-ATARM-28-Oct-04 USART Number of Errors Register Name: Access Type: 31 - 23 - 15 - 7 US_NER Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 NB_ERRORS 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. USART IrDA FILTER Register Name: Access Type: 31 - 23 - 15 - 7 US_IF Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IRDA_FILTER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 314 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Synchronous Serial Controller (SSC) Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. Transfers contain up to 16 data of up to 32 bits. They can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC's high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: * * * CODEC's in master or slave mode DAC through dedicated serial interface, particularly I2S Magnetic card reader Block Diagram Figure 131. Block Diagram ASB APB Bridge PDC APB TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 315 6070A-ATARM-28-Oct-04 Application Block Diagram Figure 132. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 316 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Pin Name List Table 70. I/O Lines Description Pin Name RF RK RD TF TK TD Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. Power Management Interrupt The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Each level of the clock must be stable for at least two master clock periods. 317 6070A-ATARM-28-Oct-04 Figure 133. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC Clock Management The transmitter clock can be generated by: * * * * * * an external clock received on the TK I/O pad the receiver clock the internal clock divider an external clock received on the RK I/O pad the transmitter clock the internal clock divider The receiver clock can be generated by: Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave-mode data transfers. 318 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Clock Divider Figure 134. Divided Clock Block diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal or greater to 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless if the DIV value is even or odd. Figure 135. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 71. Bit Rate Maximum MCK / 2 Minimum MCK / 8190 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. 319 6070A-ATARM-28-Oct-04 Figure 136. Transmitter Clock Management SSC_TCMR.CKS SSC_TCMR.CKO TK Receiver Clock Divider Clock 0 1 SSC_TCMR.CKI Transmitter Clock TK Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) might lead to unpredictable results. Figure 137. Receiver Clock Management SSC_RCMR.CKS SSC_RCMR.CKO RK Transmitter Clock Divider Clock 0 1 SSC_RCMR.CKI Receiver Clock RK 320 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See "Start" on page 322. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See "Frame Sync" on page 324. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 138. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 321 6070A-ATARM-28-Oct-04 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See "Start" on page 322. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See "Frame Sync" on page 324. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register in function of data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register, if another transfer occurs before read the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 139. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: * * * * * Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. Synchronously with the transmitter/receiver On detection of a falling/rising edge on TK/RK On detection of a low level/high level on TK/RK On detection of a level change or an edge on TK/RK A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Detection on TF/RF input/output is done through the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). 322 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Generating a Frame Sync signal is not possible without generating it on its related output. Figure 140. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 141. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 323 6070A-ATARM-28-Oct-04 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. * * Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1-bit time up to 16-bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Synchro signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register then shifted out. Frame Sync Edge Detection Th e Fra me Sync Edge de tectio n is pro gra mme d b y the FSED GE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). The data framing format of both the transmitter and the receiver are largely programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: * * * * * * The event that starts the data transfer (START). The delay in number of bit periods between the start event and the first data bit (STTDLY). The length of the data (DATLEN) The number of data to be transferred for each start event (DATNB). The length of Synchronization transferred for each start event (FSLEN). The bit sense: most or lowest significant bit first (MSBF). Additionally, the transmitter can be used to transfer Synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. Data Format 324 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table 72. Data Frame Registers Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR SSC_RCMR SSC_RCMR Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN PERIOD STTDLY up to 512 up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number Word transmitter in frame 1 most significant bit in first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 142. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF (1) Start FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of Input on falling edge of TF/RF. 325 6070A-ATARM-28-Oct-04 Figure 143. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 144. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC Controller can be programmed to generate an interrupt when it detects an event. The Interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register), which respectively enable and disable the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Interrupt 326 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 145. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 327 6070A-ATARM-28-Oct-04 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 146. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Figure 147. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In 328 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 148. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 329 6070A-ATARM-28-Oct-04 Synchronous Serial Controller (SSC) User Interface Table 73. Synchronous Serial Controller (SSC) Register Mapping Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100 - 0x124 Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Reserved Reserved Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Register Register Name SSC_CR SSC_CMR - - SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR - - SSC_RSHR SSC_TSHR - - SSC_SR SSC_IER SSC_IDR SSC_IMR - - Access Write Read/Write - - Read/Write Read/Write Read/Write Read/Write Read Write - - Read Read/Write - - Read Write Write Read - - Reset - 0x0 - - 0x0 0x0 0x0 0x0 0x0 - - - 0x0 0x0 - - 0x000000CC - - 0x0 - - 330 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SSC Control Register Name: Access Type: 31 - 23 - 15 SWRST 7 - SSC_CR Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXDIS 1 RXDIS 24 - 16 - 8 TXEN 0 RXEN * RXEN: Receive Enable 0: No effect. 1: Enables Data Receive if RXDIS is not set (1). * RXDIS: Receive Disable 0: No effect. 1: Disables Data Receive(1). * TXEN: Transmit Enable 0: No effect. 1: Enables Data Transmit if TXDIS is not set(1). * TXDIS: Transmit Disable 0: No effect. 1: Disables Data Transmit(1). * SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR. Note: 1. Only the data management is affected SSC Clock Mode Register Name: Access Type: 31 - 23 - 15 - 7 SSC_CMR Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DIV 27 - 19 - 11 3 26 - 18 - 10 DIV 2 1 0 25 - 17 - 9 24 - 16 - 8 * DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 331 6070A-ATARM-28-Oct-04 SSC Receive Clock Mode Register Name: Access Type: 31 23 15 - 7 - SSC_RCMR Read/Write 30 22 14 - 6 - 29 21 13 - 5 CKI 28 PERIOD 20 STTDLY 12 - 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 * CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock Signal RK Pin Reserved * CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2-0x7 Receive Clock Output Mode None Continuous Receive Clock Reserved RK pin Input-only Output * CKI: Receive Clock Inversion 0: The data and the Frame Sync signal are sampled on Receive Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge. CKI does not affect the RK output clock signal. 332 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit Start Detection of a low level on RF input Detection of a high level on RF input Detection of a falling edge on RF input Detection of a rising edge on RF input Detection of any level change on RF input Detection of any edge on RF input Reserved * STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. * PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 333 6070A-ATARM-28-Oct-04 SSC Receive Frame Mode Register Name: Access Type: 31 - 23 - 15 - 7 MSBF SSC_RFMR Read/Write 30 - 22 14 - 6 - 29 - 21 FSOS 13 - 5 LOOP 28 - 20 12 - 4 27 - 19 11 3 26 - 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 - 17 24 FSEDGE 16 * DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. * LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. * DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred. * FSLEN: Receive Frame Sync Length This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. Only when FSOS is set on negative or positive pulse. * FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF pin Input-only Output Output Output Output Output Undefined 334 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync sets RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 335 6070A-ATARM-28-Oct-04 SSC Transmit Clock Mode Register Name: Access Type: 31 23 15 - 7 - SSC_TCMR Read/Write 30 22 14 - 6 - 29 21 13 - 5 CKI 28 PERIOD 20 STTDLY 12 - 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 * CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved * CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Reserved TK pin Input-only Output * CKI: Transmit Clock Inversion 0: The data and the Frame Sync signal are shifted out on Transmit Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Transmit Clock rising edge. CKI affects only the Transmit Clock and not the output clock signal. 336 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled) and immediately after the end of transfer of the previous data. Receive Start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved * STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Please Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. * PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 337 6070A-ATARM-28-Oct-04 SSC Transmit Frame Mode Register Name: Access Type: 31 - 23 FSDEN 15 - 7 MSBF SSC_TFMR Read/Write 30 - 22 14 - 6 - 29 - 21 FSOS 13 - 5 DATDEF 28 - 20 12 - 4 27 - 19 11 3 26 - 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 - 17 24 FSEDGE 16 * DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. * DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. * DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start. If 0, only 1 data word is transferred and up to 16 data words can be transferred. * FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible. * FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF pin Input-only Output Output Output Output Output Undefined * FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. 338 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync sets TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 339 6070A-ATARM-28-Oct-04 SSC Receive Holding Register Name: Access Type: 31 23 15 7 SSC_RHR Read-only 30 22 14 6 29 21 13 5 28 RDAT 20 RDAT 12 RDAT 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 * RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. SSC Transmit Holding Register Name: Access Type: 31 23 15 7 SSC_THR Write only 30 22 14 6 29 21 13 5 28 TDAT 20 TDAT 12 TDAT 4 TDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 340 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SSC Receive Synchronization Holding Register Name: Access Type: 31 - 23 - 15 7 SSC_RSHR Read/Write 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 RSDAT 4 RSDAT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * RSDAT: Receive Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_RFMR. SSC Transmit Synchronization Holding Register Name: Access Type: 31 - 23 - 15 7 SSC_TSHR Read/Write 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 TSDAT 4 TSDAT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 * TSDAT: Transmit Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_TFMR. 341 6070A-ATARM-28-Oct-04 SSC Status Register Register Name: Access Type: 31 - 23 - 15 - 7 RXBUFF SSC_SR Read-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 RXEN 9 - 1 TXEMPTY 24 - 16 TXEN 8 - 0 TXRDY * TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register. 1: SSC_THR is empty. * TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from Transmit Shift Register. 1: Last data written in SSC_THR has been loaded in Transmit Shift Register and transmitted by it. * ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. * TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. * RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. * OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. * ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. * RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. * TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. * RXSYN: Receive Sync 0: A Rx Sync has not occurred since the last read of the Status Register. 1: A Rx Sync has occurred since the last read of the Status Register. 342 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * TXEN: Transmit Enable 0: Transmit data is disabled. 1: Transmit data is enabled. * RXEN: Receive Enable 0: Receive data is disabled. 1: Receive data is enabled. 343 6070A-ATARM-28-Oct-04 SSC Interrupt Enable Register Register Name: Access Type: 31 - 23 - 15 - 7 RXBUFF SSC_IER Write-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY * TXRDY: Transmit Ready * TXEMPTY: Transmit Empty * ENDTX: End of Transmission * TXBUFE: Transmit Buffer Empty * RXRDY: Receive Ready * OVRUN: Receive Overrun * ENDRX: End of Reception * RXBUFF: Receive Buffer Full * TXSYN: Tx Sync * RXSYN: Rx Sync 0: No effect. 1: Enables the corresponding interrupt. 344 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary SSC Interrupt Disable Register Register Name: Access Type: 31 - 23 - 15 - 7 RXBUFF SSC_IDR Write-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY * TXRDY: Transmit Ready * TXEMPTY: Transmit Empty * ENDTX: End of Transmission * TXBUFE: Transmit Buffer Empty * RXRDY: Receive Ready * OVRUN: Receive Overrun * ENDRX: End of Reception * RXBUFF: Receive Buffer Full * TXSYN: Tx Sync * RXSYN: Rx Sync 0: No effect. 1: Disables the corresponding interrupt. 345 6070A-ATARM-28-Oct-04 SSC Interrupt Mask Register Register Name: Access Type: 31 - 23 - 15 - 7 RXBUFF SSC_IMR Read-only 30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY * TXRDY: Transmit Ready * TXEMPTY: Transmit Empty * ENDTX: End of Transmission * TXBUFE: Transmit Buffer Empty * RXRDY: Receive Ready * OVRUN: Receive Overrun * ENDRX: End of Reception * RXBUFF: Receive Buffer Full * TXSYN: Tx Sync * RXSYN: Rx Sync 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. 346 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Timer/Counter (TC) Overview The Timer/Counter (TC) includes three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer/Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Block Diagram Figure 149. Timer/Counter Block Diagram TIMER_CLOCK1 Parallel I/O Controller TCLK0 TIOA1 TIMER_CLOCK2 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller 347 6070A-ATARM-28-Oct-04 Table 74. Signal Name Description Block/Channel Signal Name XC0, XC1, XC2 TIOA Channel Signal TIOB INT SYNC Description External Clock Inputs Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Output Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Input/output Interrupt Signal Output Synchronization Input Signal Pin Name List Table 75. TC pin list Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer/Counter clock. The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. Power Management Interrupt Functional Description TC Description 16-bit Counter The three channels of the Timer/Counter are independent and identical in operation. The registers for channel programming are listed in Table 77 on page 360. Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. 348 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 150. Each channel can independently select an internal or external clock source for its counter: * * Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock Figure 150. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 151. * The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. 349 6070A-ATARM-28-Oct-04 * The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 151. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event TC Operating Modes Each channel can independently operate in two different modes: * * Capture Mode provides measurement on signals. Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: * * Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. * The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. 350 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 152 shows the configuration of the TC channel when programmed in Capture Mode. Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 351 6070A-ATARM-28-Oct-04 Figure 152. Capture Mode 352 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS XC2 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG AT91SAM7S64 Preliminary Capture Register B Compare RC = CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6070A-ATARM-28-Oct-04 INT AT91SAM7S64 Preliminary Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 153 shows the configuration of the TC channel when programmed in Waveform Operating Mode. Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 353 6070A-ATARM-28-Oct-04 Edge Detector TIOB TC1_IMR BSWTRG Timer/Counter Channel 6070A-ATARM-28-Oct-04 INT Output Controller AT91SAM7S64 Preliminary TCCLKS CLKSTA CLKI CLKEN CLKDIS ACPC BURST Register A WAVSEL Register B Register C ASWTRG 1 16-bit Counter CLK RESET OVF Compare RA = Compare RB = Compare RC = SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG ENETRG CPCS CPAS CPBS ETRGS COVFS TC1_SR MTIOB SYNC Output Controller 354 Q CPCDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 S R ACPA MTIOA TIMER_CLOCK5 Q R CPCSTOP S XC0 XC1 Figure 153. Waveform Mode XC2 AEEVT TIOA TIOB AT91SAM7S64 Preliminary WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 154. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 155. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 154. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 155. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 355 6070A-ATARM-28-Oct-04 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 156. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 157. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 156. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 157. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 356 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 158. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 159. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 158. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 159. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 357 6070A-ATARM-28-Oct-04 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 160. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 161. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 160. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 161. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 358 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 359 6070A-ATARM-28-Oct-04 Timer/Counter (TC) User Interface Global Register Mapping Table 76. Timer/Counter (TC) Global Register Map Offset 0x00 0x40 0x80 0xC0 0xC4 Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 77 See Table 77 See Table 77 Write-only Read/Write - 0 Reset Value TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 77. The offset of each of the channel registers in Table 77 is in relation to the offset of the corresponding channel as mentioned in Table 77. Channel Memory Mapping Table 77. Timer/Counter (TC) Channel Memory Mapping Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30-0xFC Note: Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Name TC_CCR TC_CMR - - TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR - Access Write-only Read/Write - - Read-only Read/Write(1) Read/Write (1) Reset Value - 0 - - 0 0 0 0 0 - - 0 - Read/Write Read-only Write-only Write-only Read-only - 1. Read only if WAVE = 0 360 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TC Block Control Register Register Name: TC_BCR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 SYNC * SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. TC Block Mode Register Register Name: TC_BMR Access Type: 31 - 23 - 15 - 7 - Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 TC2XC2S 28 - 20 - 12 - 4 27 - 19 - 11 - 3 TCXC1S 26 - 18 - 10 - 2 25 - 17 - 9 - 1 TC0XC0S 24 - 16 - 8 - 0 * TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 * TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 361 6070A-ATARM-28-Oct-04 * TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 TC Channel Control Register Register Name: TC_CCR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SWTRG 25 - 17 - 9 - 1 CLKDIS 24 - 16 - 8 - 0 CLKEN * CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. * CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. * SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 362 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: 31 - 23 - 15 WAVE = 0 7 LDBDIS Read/Write 30 - 22 - 14 CPCTRG 6 LDBSTOP 29 - 21 - 13 - 5 BURST 28 - 20 - 12 - 4 11 - 3 CLKI 27 - 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 - 18 25 - 17 LDRA 8 24 - 16 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. * LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 363 6070A-ATARM-28-Oct-04 * ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). * LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA * LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 364 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: 31 BSWTRG 23 ASWTRG 15 WAVE = 1 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS Read/Write 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 * TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 * CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. * CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. * CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 365 6070A-ATARM-28-Oct-04 * EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge * EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. * ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. * WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare * WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. * ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle * ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle 366 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle * ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle * BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle * BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle * BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle * BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 367 6070A-ATARM-28-Oct-04 TC Counter Value Register Register Name: TC_CV Access Type: 31 - 23 - 15 Read-only 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CV 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 CV 3 2 1 0 * CV: Counter Value CV contains the counter value in real time. TC Register A Register Name: TC_RA Access Type: 31 - 23 - 15 Read-only if WAVE = 0, Read/Write if WAVE = 1 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RA 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RA 3 2 1 0 * RA: Register A RA contains the Register A value in real time. 368 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TC Register B Register Name: TC_RB Access Type: 31 - 23 - 15 Read-only if WAVE = 0, Read/Write if WAVE = 1 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RB 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RB 3 2 1 0 * RB: Register B RB contains the Register B value in real time. TC Register C Register Name: TC_RC Access Type: 31 - 23 - 15 Read/Write 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RC 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8 7 6 5 4 RC 3 2 1 0 * RC: Register C RC contains the Register C value in real time. 369 6070A-ATARM-28-Oct-04 TC Status Register Register Name: TC_SR Access Type: 31 - 23 - 15 - 7 ETRGS Read-only 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 MTIOB 10 - 2 CPAS 25 - 17 MTIOA 9 - 1 LOVRS 24 - 16 CLKSTA 8 - 0 COVFS * COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. * LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. * CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. * LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. * LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. * ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. * CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. * MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. * MTIOB: TIOB Mirror 370 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 371 6070A-ATARM-28-Oct-04 TC Interrupt Enable Register Register Name: TC_IER Access Type: 31 - 23 - 15 - 7 ETRGS Write-only 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. * CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. * CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. * CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. * LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. * ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 372 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary TC Interrupt Disable Register Register Name: TC_IDR Access Type: 31 - 23 - 15 - 7 ETRGS Write-only 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). * CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). * CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). * CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). * LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). * ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 373 6070A-ATARM-28-Oct-04 TC Interrupt Mask Register Register Name: TC_IMR Access Type: 31 - 23 - 15 - 7 ETRGS Read-only 30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS * COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. * LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. * CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. * CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. * CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. * LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. * LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. * ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 374 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Pulse Width Modulation Controller (PWM) Overview The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. Block Diagram Figure 162. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Channel Period Update Duty Cycle Comparator PWMx PWMx Clock Selector Counter PIO PWM0 Channel Period Update Duty Cycle Comparator PWM0 PWM0 Clock Selector MCK Counter PMC Clock Generator APB Interface Interrupt Generator AIC APB 375 6070A-ATARM-28-Oct-04 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 78. I/O Line Description Name Description Type Output PWMx PWM Waveform Output for channel x Product Dependencies I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled. Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode. 376 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. - - - Clocked by the system clock, MCK, the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. PWM Clock Generator Figure 163. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A clkA PREA DIVA PWM_MR Divider B clkB PREB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: - - a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM 377 6070A-ATARM-28-Oct-04 Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock "clk". This situation is also true when the PWM master clock is turned off through the Power Management Controller. PWM Channel Block Diagram Figure 164. Functional View of the Channel Block Diagram Inputs from clock generator Channel Clock Selector Inputs from APB Bus Internal Counter Comparator PWMx output waveform Each of the 4 channels is composed of three blocks: * * A clock selector which selects one of the clocks provided by the clock generator described in Section "PWM Clock Generator" on page 377. An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 16 bits. A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration. * Waveform Properties The different properties of output waveforms are: * the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be claculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: ( X x CPRD ) -----------------------------MCK * By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( CRPD x DIVAB ) ( CRPD x DIVA ) ----------------------------------------- or --------------------------------------------MCK MCK If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: 378 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 x X x CPRD ) ---------------------------------------MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 x CPRD x DIVB ) ( 2 x CPRD x DIVA ) --------------------------------------------------- or --------------------------------------------------MCK MCK * the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: ( period - 1 fchannel_x_clock x CDTY ) duty cycle = ------------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: ( ( period 2 ) - 1 fchannel_x_clock x CDTY ) ) duty cycle = ---------------------------------------------------------------------------------------------------------------------( period 2 ) * the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level. the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. * Figure 165. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 166 on page 381 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and .decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when: * CDTY = CPRD and CPOL = 0 379 6070A-ATARM-28-Oct-04 * * * CDTY = 0 and CPOL = 1 CDTY = 0 and CPOL = 0 CDTY = CPRD and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when: The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled. 380 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 166. Waveform Properties PWM_MCKx CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Left Aligned CALG(PWM_CMRx) = 0 Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) 381 6070A-ATARM-28-Oct-04 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: * * * * Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx register) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below. Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below. Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) Enable Interrupts (Writing CHIDx in the PWM_IER register) Enable the PWM channel (Writing CHIDx in the PWM_ENA register) * * * * It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. * In such a situation, all channels may have the same clock selector configuration and the same period specified. Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period. Changing the Duty Cycle or the Period It is possible to modulate the output waveform duty cycle or period. To prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, PWM_CPRDx and PWM_CDTYx registers are double buffered. Th e user can write a new pe riod value or du ty cycle value in the upda te re gister (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. According to the CPD field in the PWM_CMRx register, PWM_CUPDx either updates the PWM_CPRDx or PWM_CDTYx. 382 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 167. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 1 0 PWM_CMRx. CPD PWM_CPRDx PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 168. The second method uses an Interrupt Service Routine associated with the PWM channel. Note: Reading the PWM_ISR register automatically clears CHIDx flags. Figure 168. Polling Method PWM_ISR Read Acknowledgement and clear previous register state Writing in CPD field Update of the Period or Duty Cycle CHIDx = 1 YES Writing in PWM_CUPDx The last write has been taken into account 383 6070A-ATARM-28-Oct-04 PWM User Interface PWM Register Mapping Table 79. PWM Controller Registers Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x4C - 0xF8 0xFC 0x100 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 ... 0x220 0x224 0x228 0x22C 0x230 ... Note: Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved Version Register Reserved Channel 0 Mode Register Channel 0 Duty Cycle Register Channel 0 Period Register Channel 0 Counter Register Channel 0 Update Register Reserved Channel 1 Mode Register Channel 1 Duty Cycle Register Channel 1 Period Register Channel 1 Counter Register Channel 1 Update Register ... PWM_CMR1 PWM_CDTY1 PWM_CPRD1 PWM_CCNT1 PWM_CUPD1 ... Read/Write Read/Write Read/Write Read-only Write-only ... 0x0 0x0 0x0 0x0 ... PWM_CMR0 PWM_CDTY0 PWM_CPRD0 PWM_CCNT0 PWM_CUPD0 Read/Write Read/Write Read/Write Read-only Write-only 0x0 0x0 0x0 0x0 Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR - PWM_VERSION Access Read/Write Write-only Write-only Read-only Write-only Write-only Read-only Read-only - Read-only Peripheral Reset Value 0 0 0 0 - 0x- (1) 1. Values in the Version Register vary with the version of the IP block implementation. 384 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PWM Mode Register Register Name: PWM_MR Access Type: 31 - 23 Read/Write 30 - 22 29 - 21 28 - 20 DIVB 27 26 PREB 19 18 17 16 25 24 15 - 7 14 - 6 13 - 5 12 - 4 DIVA 11 10 PREA 9 8 3 2 1 0 * DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB 0 1 2-255 CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. * PREA, PREB PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK. MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved Divider Input Clock 385 6070A-ATARM-28-Oct-04 PWM Enable Register Register Name: PWM_ENA Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. PWM Disable Register Register Name: PWM_DIS Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x. 386 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PWM Status Register Register Name: PWM_SR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 387 6070A-ATARM-28-Oct-04 PWM Interrupt Enable Register Register Name: PWM_IER Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. PWM Interrupt Disable Register Register Name: PWM_IDR Access Type: 31 - 23 - 15 - 7 - Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x. 388 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PWM Interrupt Mask Register Register Name: PWM_IMR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. PWM Interrupt Status Register Register Name: PWM_ISR Access Type: 31 - 23 - 15 - 7 - Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0 * CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register. Note: Reading PWM_ISR automatically clears CHIDx flags. 389 6070A-ATARM-28-Oct-04 PWM Channel Mode Register Register Name: PWM_CMRx Access Type: 31 - 23 - 15 - 7 - Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 26 - 18 - 10 CPD 2 CPRE 25 - 17 - 9 CPOL 1 24 - 16 - 8 CALG 0 * CPRE: Channel Pre-scaler CPRE 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved Channel Pre-scaler * CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. * CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. * CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event. 390 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PWM Channel Duty Cycle Register Register Name: PWM_CDTYx Access Type: 31 Read/Write 30 29 28 CDTY 27 26 25 24 23 22 21 20 CDTY 19 18 17 16 15 14 13 12 CDTY 11 10 9 8 7 6 5 4 CDTY 3 2 1 0 Only the first 16 bits (internal channel counter size) are significative. * CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 391 6070A-ATARM-28-Oct-04 PWM Channel Period Register Register Name: PWM_CPRDx Access Type: 31 Read/Write 30 29 28 CPRD 27 26 25 24 23 22 21 20 CPRD 19 18 17 16 15 14 13 12 CPRD 11 10 9 8 7 6 5 4 CPRD 3 2 1 0 Only the first 16 bits (internal channel counter size) are significative. * CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( X x CPRD ) -----------------------------MCK - By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( CRPD x DIVAB ) ( CRPD x DIVA ) ----------------------------------------- or --------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the counter source clockand can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 x X x CPRD ) ---------------------------------------MCK - By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 x CPRD x DIVB ) ( 2 x CPRD x DIVA ) --------------------------------------------------- or --------------------------------------------------MCK MCK 392 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PWM Channel Counter Register Register Name: PWM_CCNTx Access Type: 31 Read-only 30 29 28 CNT 27 26 25 24 23 22 21 20 CNT 19 18 17 16 15 14 13 12 CNT 11 10 9 8 7 6 5 4 CNT 3 2 1 0 * CNT: Channel Counter Register Internal counter value. This register is reset when: * * the channel is enabled (writing CHIDx in the PWM_ENA register). the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. PWM Channel Update Register Register Name: PWM_CUPDx Access Type: 31 Write-only 30 29 28 CUPD 27 26 25 24 23 22 21 20 CUPD 19 18 17 16 15 14 13 12 CUPD 11 10 9 8 7 6 5 4 CUPD 3 2 1 0 This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 16 bits (internal channel counter size) are significative. CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period. 393 6070A-ATARM-28-Oct-04 PWM Version Register Register Name: Access Type: 31 - 23 - 15 - 7 PWM_VERSION Read-only 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 VERSION 3 2 27 - 19 - 11 10 VERSION 1 0 26 - 18 25 - 17 MFN 9 8 24 - 16 * VERSION Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell. * MFN Reserved. Value subject to change. No functionality associated. 394 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Device Port (UDP) Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 80. USB Endpoint Description Endpoint Number 0 1 3 3 Mnemonic EP0 EP1 EP2 EP3 Dual-Bank No Yes Yes No Max. Endpoint Size 8 64 64 64 Endpoint Type Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Control/Bulk/Interrupt Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake-up to the USB host controller. Block Diagram Figure 169. Block Diagram Atmel Bridge APB to MCU Bus USB Device txoen MCK UDPCK U s e r I n t e r f a c e W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz txd rxdm rxd rxdp Embedded USB Transceiver DP DM SIE udp_int Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain external_resume 395 6070A-ATARM-28-Oct-04 Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake-up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration. Product Dependencies For further details on the USB Device hardware implementation, see "USB Device Port" on page 28. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. Two I/O lines may be used by the application: * One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the board pull-up on DP must be disabled in order to prevent feeding current to the host. One to control the board pull-up on DP. Thus, when the device is ready to communicate with the host, it activates its DP pull-up through this control line. * I/O Lines DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode. To reserve an I/O line to control the board pull-up, the programmer must first program the PIO controller to assign this I/O in output PIO mode. Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain). Interrupt The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP. 396 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Typical Connection Figure 170. Board Schematic to Interface USB Device Peripheral PAm USB_CNX 15 k 22 k 3V3 1.5 k 47 k PAn USB_DP_PUP System Reset 27 DM DP 15 pF 15 pF 33 pF 2 1 100 nF Type B 4 Connector 27 3 USB_CNX is an input signal used to check if the host is connected USB_DP_PUP is an output signal used to enable pull-up on DP. Figure 170 shows automatic activation of pull-up after reset. 397 6070A-ATARM-28-Oct-04 Functional Description USB V2.0 Fullspeed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with an USB device through a set of communication flows. Figure 171. Example of USB V2.0 Full-speed Communication Control USB Host V2.0 Software Client 1 Software Client 2 Data Flow: Control Transfer Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer EP0 EP1 EP2 USB Device 2.0 Block 1 Data Flow: Control Transfer Data Flow: Bulk In Transfer Data Flow: Bulk Out Transfer EP0 EP4 EP5 USB Device 2.0 Block 2 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. Table 81. USB Communication Flow Transfer Control Isochronous Interrupt Bulk Direction Bi-directional Uni-directional Uni-directional Uni-directional Bandwidth Not guaranteed Guaranteed Not guaranteed Not guaranteed Endpoint Size 8, 16, 32, 64 1 - 1023 64 8, 16, 32, 64 Error Detection Yes Yes Yes Yes Retrying Automatic No Yes Yes USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 4. Status IN Transaction 5. Status OUT Transaction 398 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 82. USB Transfer Events Control Transfers(1) (3) * * * * * * * * * Setup transaction > Data IN transactions > Status OUT transaction Setup transaction > Data OUT transactions > Status IN transaction Setup transaction > Status IN transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: * * * The USB device automatically acknowledges the setup packet RXSETUP is set in the USB_CSRx register An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the USB_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 399 6070A-ATARM-28-Oct-04 Figure 172. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (USB_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. To perform a Data IN transaction using a non ping-pong endpoint: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint's USB_CSRx register (TXPKTRDY must be cleared). 2. The microcontroller writes data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's USB_FDRx register, 3. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's USB_CSRx register. 4. The microcontroller is notified that the endpoint's FIFO has been released by the USB device when TXCOMP in the endpoint's USB_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. Using Endpoints Without Ping-pong Attributes 400 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 173. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (USB_CSRx) Cleared by USB Device Interrupt Pending TXCOMP Flag (USB_CSRx) Cleared by Firmware Set by the Firmware Data Payload Written in FIFO Start to Write Data Payload in FIFO Interrupt Pending FIFO (DPR) Content Data IN 1 Load In Progress Data IN 2 Load In Progress Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 174. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller 1st Data Payload Write Bank 0 Endpoint 1 USB Device Read USB Bus Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint's USB_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint's USB_FDRx register. 401 6070A-ATARM-28-Oct-04 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint's USB_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint's USB_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint's USB_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint's USB_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 175. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (USB_MCSRx) Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (USB_CSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth. Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once Data OUT Transaction Without Ping-pong Attributes 402 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint's USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's USB_CSRx register. 5. The microcontroller carries out data received from the endpoint's memory to its memory. Data received is available by reading the endpoint's USB_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's USB_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 176. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 Data OUT2 NAK PID PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (USB_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. 403 6070A-ATARM-28-Oct-04 Figure 177. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint's FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint's USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's USB_CSRx register. 6. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is made available by reading the endpoint's USB_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's USB_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint's USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is available by reading the endpoint's USB_FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint's USB_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. 404 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Figure 178. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (USB_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (USB_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. Status Transaction A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 405 6070A-ATARM-28-Oct-04 Figure 179. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Notes: Setup TX Status IN TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). Status IN Transfer Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction. 1. The microcontroller waits for TXPKTRDY in the USB_CSRx endpoint's register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.) 2. Without writing anything to the USB_FDRx endpoint's register, the microcontroller sets TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID. 3. This packet is acknowledged by the host and TXPKTRDY is set in the USB_CSRx endpoint's register. Figure 180. Data Out Followed by Status IN Transfer. Host Sends the Last Data Payload to the Device USB Bus Packets Device Sends a Status IN to the Host Data OUT PID Data OUT NAK PID Data IN PID ACK PID Interrupt Pending RX_DATA_BKO (USB_CSRx) Cleared by Firmware Set by USB Device Cleared by USB Device TXPKTRDY (USB_CSRx) Set by Firmware 406 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Status OUT Transfer Once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction. 1. The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the USB_CSRx register and acknowledges the zero length packet. 2. The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the USB_CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint's USB_BCR register is equal to zero. 3. The microcontroller must clear RX_DATA_BK0. Figure 181. Data IN Followed by Status OUT Transfer Device Sends the Last Data Payload to Host USB Bus Packets Data IN PID Data IN ACK PID Device Sends a Status OUT to Host Data OUT PID ACK PID Interrupt Pending RX_DATA_BKO (USB_CSRx) Set by USB Device Cleared by Firmware TXCOMP (USB_CSRx) Set by USB Device Cleared by Firmware Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) * A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) To abort the current request, a protocol stall is used, but uniquely with control transfer. * The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the USB_CSRx endpoint's register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. 407 6070A-ATARM-28-Oct-04 Figure 182. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 183. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 408 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 184. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the UDP device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 A on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host. 409 6070A-ATARM-28-Oct-04 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device's pull-up on DP. The unmasked flag ENDBURST is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. After a set address standard device request, the USB host peripheral enters the address state. Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To m ove to address s tate, t he driv er sof tware set s the FA DDEN f lag in t he UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register. From Default State to Address State From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected. Enabling Suspend Receiving a Host Resume In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous. Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. Sending an External Resume The External Resume is negotiated with the host and enabled by setting the ESR bit in the USB_GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the ho st very q uickly . On r ece nt ver sio ns, the softwa re se ts the R MWU PE bit in th e UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 410 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Device Port (UDP) User Interface Table 83. USB Device Port (UDP) Register Mapping Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 . . . See Note 1 0x050 . . . See Note 2 0x070 0x074 0x078 - 0x0FC Notes: Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register . . . Endpoint 3 Control and Status Register Endpoint 0 FIFO Data Register . . . Endpoint 3 FIFO Data Register Reserved Transceiver Control Register Reserved USB_FDR3 - USB_TXVC - Read/Write - Read/Write - 0x0000_0000 - 0x0000_0100 - USB _CSR3 USB_FDR0 Read/Write Read/Write 0x0000_0000 0x0000_0000 Name USB_FRM_NUM USB_GLB_STAT USB_FADDR - USB_IER USB_IDR USB_IMR USB_ISR USB_ICR - USB_RST_EP - USB _CSR0 Access Read Read/Write Read/Write - Write Write Read Read Write - Read/Write - Read/Write - 0x0000_0000 - 0x0000_1200 0x0000_0000 Reset State 0x0000_0000 0x0000_0010 0x0000_0100 - 1. The addresses of the USB_CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1). 2. The addresses of the USB_FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1). 411 6070A-ATARM-28-Oct-04 USB Frame Number Register Register Name: Access Type: 31 --23 - 15 - 7 USB_FRM_NUM Read-only 30 --22 - 14 - 6 29 --21 - 13 - 5 28 --20 - 12 - 4 FRM_NUM 27 --19 - 11 - 3 26 --18 - 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 2 0 * FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). * FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. * FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 412 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Global State Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_GLB_STAT Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 RMWUPE 27 - 19 - 11 - 3 RSMINPR 26 - 18 - 10 - 2 ESR 25 - 17 - 9 - 1 CONFG 24 - 16 - 8 - 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. * FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the USB_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * ESR: Enable Send Resume 0 = Disables the Remote Wake Up sequence. 1 = Remote Wake Up can be processed and the pin send_resume is enabled. * RSMINPR: A Resume Has Been Sent to the Host Read: 0 = No effect. 1 = A Resume has been received from the host during Remote Wake Up feature. * RMWUPE: Remote Wake Up Enable 0 = Must be cleared after receiving any HOST packet or SOF interrupt. 1 = Enables the K-state on the USB cable if ESR is enabled. 413 6070A-ATARM-28-Oct-04 USB Function Address Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_FADDR Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 FADD 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 FEN 0 * FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. * FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 414 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Interrupt Enable Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_IER Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 28 - 20 - 12 - 4 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Enable Endpoint 0 Interrupt * EP1INT: Enable Endpoint 1 Interrupt * EP2INT: Enable Endpoint 2Interrupt * EP3INT: Enable Endpoint 3 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. * RXSUSP: Enable USB Suspend Interrupt 0 = No effect. 1 = Enables USB Suspend Interrupt. * RXRSM: Enable USB Resume Interrupt 0 = No effect. 1 = Enables USB Resume Interrupt. * EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. * SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. * WAKEUP: Enable USB bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 415 6070A-ATARM-28-Oct-04 USB Interrupt Disable Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_IDR Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 28 - 20 - 12 - 4 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Disable Endpoint 0 Interrupt * EP1INT: Disable Endpoint 1 Interrupt * EP2INT: Disable Endpoint 2 Interrupt * EP3INT: Disable Endpoint 3 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. * RXSUSP: Disable USB Suspend Interrupt 0 = No effect. 1 = Disables USB Suspend Interrupt. * RXRSM: Disable USB Resume Interrupt 0 = No effect. 1 = Disables USB Resume Interrupt. * EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. * SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt * WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 416 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Interrupt Mask Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_IMR Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 28 - 20 - 12 - 4 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Mask Endpoint 0 Interrupt * EP1INT: Mask Endpoint 1 Interrupt * EP2INT: Mask Endpoint 2 Interrupt * EP3INT: Mask Endpoint 3 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. * RXSUSP: Mask USB Suspend Interrupt 0 = USB Suspend Interrupt is disabled. 1 = USB Suspend Interrupt is enabled. * RXRSM: Mask USB Resume Interrupt. 0 = USB Resume Interrupt is disabled. 1 = USB Resume Interrupt is enabled. * EXTRSM: Mask External Resume Interrupt 0 = External Resume Interrupt is disabled. 1 = External Resume Interrupt is enabled. * SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. * WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register USB_IMR is enabled. 417 6070A-ATARM-28-Oct-04 USB Interrupt Status Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_ISR Read-only 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 28 - 20 - 12 ENDBUSRES 4 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 EXTRSM 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT * EP0INT: Endpoint 0 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit. * EP1INT: Endpoint 1 Interrupt Status 0 = No Endpoint1 Interrupt pending. 1 = Endpoint1 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR1: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit. * EP2INT: Endpoint 2 Interrupt Status 0 = No Endpoint2 Interrupt pending. 1 = Endpoint2 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR2: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 418 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit. * EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint3 Interrupt pending. 1 = Endpoint3 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR3: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit. * RXSUSP: USB Suspend Interrupt Status 0 = No USB Suspend Interrupt pending. 1 = USB Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. * RXRSM: USB Resume Interrupt Status 0 = No USB Resume Interrupt pending. 1 =USB Resume Interrupt has been raised. The USB device sets this bit when a USB resume signal is detected at its port. * EXTRSM: External Resume Interrupt Status 0 = No External Resume Interrupt pending. 1 = External Resume Interrupt has been raised. This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus. * SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. * ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a USB reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. * WAKEUP: USB Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. 419 6070A-ATARM-28-Oct-04 USB Interrupt Clear Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_ICR Write-only 30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 - 28 - 20 - 12 ENDBURST 4 - 27 - 19 - 11 SOFINT 3 - 26 - 18 - 10 EXTRSM 2 - 25 - 17 - 9 RXRSM 1 - 24 - 16 - 8 RXSUSP 0 - * RXSUSP: Clear USB Suspend Interrupt 0 = No effect. 1 = Clears USB Suspend Interrupt. * RXRSM: Clear USB Resume Interrupt 0 = No effect. 1 = Clears USB Resume Interrupt. * EXTRSM: Clear External Resume Interrupt 0 = No effect. 1 = Clears External Resume Interrupt. * SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. * ENDBURST: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. * WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 420 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary USB Reset Endpoint Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_RST_EP Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 EP3 26 - 18 - 10 - 2 EP2 25 - 17 - 9 - 1 EP1 24 - 16 - 8 - 0 EP0 * EP0: Reset Endpoint 0 * EP1: Reset Endpoint 1 * EP2: Reset Endpoint 2 * EP3: Reset Endpoint 3 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear USB_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in USB_CSRx register. 421 6070A-ATARM-28-Oct-04 USB Endpoint Control and Status Register Register Name: Access Type: 31 - 23 USB_CSRx [x = 0..3] Read/Write 30 - 22 29 - 21 28 - 20 RXBYTECNT 27 - 19 26 25 RXBYTECNT 17 24 18 16 15 EPEDS 7 DIR 14 - 6 RX_DATA_ BK1 13 - 5 FORCE STALL 12 - 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 2 RXSETUP 0 TXCOMP * TXCOMP: Generates an IN packet with data previously written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. * RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the USB_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. * RXSETUP: Sends STALL to the Host (Control Endpoints) This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 422 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the USB_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transactions is not accepted while RXSETUP is set. * STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. * TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Data values can be written in the FIFO. 1 = Data values can not be written in the FIFO. Write: 0 = No effect. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the USB_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. * FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Write-only 0 = No effect. 1 = Sends STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. 423 6070A-ATARM-28-Oct-04 Control endpoints: During the data stage and status stage, this indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: Notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. * RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO's Bank 1. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through USB_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. * DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before USB_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. * EPTYPE[2:0]: Endpoint Type Read/Write 000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN * DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. 424 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary * EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. * RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the USB_FDRx register. USB FIFO Data Register Register Name: Access Type: 31 - 23 - 15 - 7 USB_FDRx [x = 0..3] Read/Write 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FIFO_DATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 * FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding USB_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 425 6070A-ATARM-28-Oct-04 USB Transceiver Control Register Register Name: Access Type: 31 - 23 - 15 - 7 - USB_TXVC Read/Write 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 TXVDIS 0 - * TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. 426 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Analog-to-digital Converter (ADC) Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analogto-digital conversions of up to eight analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time. Block Diagram Figure 185. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC Trigger Selection ADTRG Control Logic ADC Interrupt AIC VDDIN ADVREF ASB AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Successive Approximation Register Analog-to-Digital Converter APB PIO User Interface Peripheral Bridge PDC 427 6070A-ATARM-28-Oct-04 Signal Description Table 84. ADC Pin Description Pin Name VDDIN ADVREF AD0 - AD7 ADTRG Description Analog power supply Reference voltage Analog input channels External trigger Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior. The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. The pins AD0 to AD7 can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pullup enabled and the ADC input is connected to the GND. The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. For performance and electrical characteristics of the ADC, see "ADC Characteristics" on page 453. Interrupt Sources Analog Inputs I/O Lines Timer Triggers Conversion Performances 428 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the "ADC Mode Register" on page 435 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section. Conversion Reference Conversion Resolution The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0. Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. 429 6070A-ATARM-28-Oct-04 Figure 186. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) Conversion Time Conversion Time DRDY (ADC_SR) 430 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 187. GOVRE and OVREx Flag Behavior ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Read ADC_SR Data C Data B EOC0 (ADC_SR) Conversion Conversion Read ADC_CDR0 EOC1 (ADC_SR) Conversion Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR). 431 6070A-ATARM-28-Oct-04 If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channe l Disab le (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR. The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section DC Characteristics in the product datasheet. 432 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Analog-to-digital Converter (ADC) User Interface Table 85. ADC Register Mapping Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 - 0xFC Register Control Register Mode Register Reserved Reserved Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 Channel Data Register 2 Channel Data Register 3 Channel Data Register 4 Channel Data Register 5 Channel Data Register 6 Channel Data Register 7 Reserved Name ADC_CR ADC_MR - - ADC_CHER ADC_CHDR ADC_CHSR ADC_SR ADC_LCDR ADC_IER ADC_IDR ADC_IMR ADC_CDR0 ADC_CDR1 ADC_CDR2 ADC_CDR3 ADC_CDR4 ADC_CDR5 ADC_CDR6 ADC_CDR7 - Access Write-only Read/Write - - Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only - Reset State - 0x00000000 - - - - 0x00000000 0x000C0000 0x00000000 - - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - 433 6070A-ATARM-28-Oct-04 ADC Control Register Register Name:ADC_CR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - - - - - - START SWRST * SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. * START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. 434 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary ADC Mode Register Register Name:ADC_MR Access Type:Read/Write 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 19 18 SHTIM 17 16 - 15 - 14 - 13 12 11 STARTUP 10 9 8 - 7 - 6 5 4 3 PRESCAL 2 1 0 - - SLEEP LOWRES TRGSEL TRGEN * TRGEN: Trigger Enable TRGEN 0 1 Selected TRGEN Hardware triggers are disabled. Starting a conversion is only possible by software. Hardware trigger selected by TRGSEL field is enabled. * TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected TRGSEL TIOA Ouput of the Timer Counter Channel 0 TIOA Ouput of the Timer Counter Channel 1 TIOA Ouput of the Timer Counter Channel 2 Reserved Reserved Reserved External trigger Reserved * LOWRES: Resolution LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution * SLEEP: Sleep Mode SLEEP 0 1 Selected Mode Normal Mode Sleep Mode * PRESCAL: Prescaler Rate Selection 435 6070A-ATARM-28-Oct-04 ADCClock = MCK / ( (PRESCAL+1) * 2 ) * STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock * SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock 436 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary ADC Channel Enable Register Register Name:ADC_CHER Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 * CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. ADC Channel Disable Register Register Name:ADC_CHDR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 * CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 437 6070A-ATARM-28-Oct-04 ADC Channel Status Register Register Name:ADC_CHSR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 * CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 438 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary ADC Status Register Register Name:ADC_SR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. * OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR. * DRDY: Data Ready 0 = No data has been converted since the last read of ADC_LCDR. 1 = At least one data has been converted and is available in ADC_LCDR. * GOVRE: General Overrun Error 0 = No Overrun Error occurred since the last read of ADC_SR. 1 = At least one Overrun Error has occurred since the last read of ADC_SR. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR. * RXBUFF: RX Buffer Full 0 = ADC_RCR or ADC_RNCR have a value other than 0. 1 = Both ADC_RCR and ADC_RNCR have a value of 0. 439 6070A-ATARM-28-Oct-04 ADC Last Converted Data Register Register Name:ADC_LCDR Access Type:Read-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 LDATA 0 LDATA * LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 440 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary ADC Interrupt Enable Register Register Name:ADC_IER Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion Interrupt Enable x * OVREx: Overrun Error Interrupt Enable x * DRDY: Data Ready Interrupt Enable * GOVRE: General Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 441 6070A-ATARM-28-Oct-04 ADC Interrupt Disable Register Register Name:ADC_IDR Access Type:Write-only 31 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 * EOCx: End of Conversion Interrupt Disable x * OVREx: Overrun Error Interrupt Disable x * DRDY: Data Ready Interrupt Disable * GOVRE: General Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 442 AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary AT91SAM7S64 Electrical Characteristics Absolute Maximum Ratings Table 86. Absolute Maximum Ratings* Operating Temperature (Industrial)...... -40C to +85C Storage Temperature ......................... -60C to +150C Voltage on Input Pins with Respect to Ground .........................-0.3V to +5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL) ................................ 1.95V Maximum Operating Voltage (VDDIO, VDDIN and VDDFLASH)........................ 3.6V Total DC Output Current on all I/O lines .......... 150 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 443 6070A-ATARM-28-Oct-04 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Table 87. DC Characteristics Symbol VVDDCORE VVDDPLL VVDDIO VVDDFLASH VIL VIH VOL VOH ILEAK IPULLUP C IN Parameter DC Supply Core DC Supply PLL DC Supply I/Os DC Supply Flash Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage Input Leakage Current Input Pull-up Current Input Capacitance 64-LQFP Package VVDDCORE = 1.85V, MCK = 0 Hz ISC Static Current All inputs driven at 1 (including TMS, TDI, TCK, NRST) PA0-PA3 IO Output Current PA4-PA31 8 mA TA =25C 26 IO = 8 mA IO = 8 mA Pull-up resistors disabled (Typ: TA = 25C, Max: TA = 85C) 143 VDDIO - 0.4 20 321 200 600 13.9 50 A TA = 85C 260 500 16 mA Conditions Min 1.65 1.65 3.0 3.0 -0.3 2.0 Typ Max 1.95 1.95 3.6 3.6 0.8 5.5 0.4 Units V V V V V V V V nA A pF Table 88. 1.8V Voltage Regulator Characteristics Symbol VVDDIN VVDDOUT IVDDIN Parameter Supply Voltage Output Voltage Current consumption After startup, no load During startup, no load Idle mode TSTART IO IO Startup Time Maximum DC Output Current Maximum DC Output Current Cload = 2.2 F, after VDDIN > 2.7V VDDIN = 3.3V VDDIN = 3.3V, in Idle Mode Conditions Min 3.0 1.81 Typ 3.3 1.85 90 100 20 150 100 1 Max 3.6 1.89 Units V V A mA A S mA mA 444 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Table 89. Brownout Detector Characteristics Symbol VBOTVHYST IDD TSTART Parameter Threshold Level Hysteresis Current Consumption BOD off (GPNVM0 bit inactive) Startup Time 100 1 200 mA ms VHYST = VBOT+ - VBOTBOD on (GPNVM0 bit active) Conditions Min 1.65 Typ 1.68 50 12 Max 1.71 65 18 Units V mV A 445 6070A-ATARM-28-Oct-04 Power Consumption * * * Typical power consumption of PLLs, Slow Clock and Main Oscillator. Power consumption of power supply in two different modes: Active and ultra Low-power. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. Power Consumption Versus Modes The values in Table 90 and Table 91 on page 448 are estimated values of the power consumption with operating conditions as follows: * * * * * VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25C MCK = 50 MHz There is no consumption on the I/Os of the device Figure 188. Measure Schematics: VDDFLASH VDDIO 3.3V AMP1 VDDIN Voltage Regulator VDDOUT 1.8V AMP2 VDDCORE VDDPLL 446 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary These figures represent the power consumption estimated on the power supplies.. Table 90. Power Consumption for Different Modes Mode Active Conditions Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. onto AMP1 onto AMP2 Ultra low power Voltage regulator is in Low-power mode. Brown Out Detector is de-activated. Flash is in standby mode. ARM Core clock is 500Hz. Analog-to-Digital Converter de-activated. All peripheral clocks de-activated. onto AMP1 onto AMP2 31.3 29.3 mA Consumption Unit 36.2 35.2 A 447 6070A-ATARM-28-Oct-04 Peripheral Power Consumption in Active Mode Table 91. Power Consumption by Peripheral Peripheral PIO Controller USART ADC PWM TWI SPI SSC Timer Counter Channels Consumption 0.4 0.9 0.7 0.3 mA 0.2 0.9 1.1 0.2 Unit 448 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Power Consumption versus Master Clock Frequency in Active Mode Figure 189 produces estimated values with operating conditions as follows: * * * * * * * * * * VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25C MCK in the MHz range Voltage regulator is on Brown-out Detector is activated Flash is read Analog-to-Digital Converter activated All peripheral clocks activated There is no consumption on the I/Os of the device Figure 189 presents the power consumption estimated on the power supply. Figure 189. Power Consumption versus MCK Frequency in Active Mode Current Consumption at 3.3V 100,000 31,278 16,219 8,685 4,918 1,622 2,063 3,035 1,000 10,000 Consumption (A) 100 0.78125 1.5625 3.125 6.25 12.5 25 50 Frequency (MHz) 449 6070A-ATARM-28-Oct-04 Power Consumption versus Master Clock Frequency in Ultra Low-power Mode Figure 190 produces estimated values with operating conditions as follows: * * * * * * * * * * * VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25C Voltage regulator is in Low-power mode Brown Out Detector is de-activated Flash is in standby mode Analog-to-digital Converter de-activated All peripheral clocks de-activated PLL in standby Main oscillator in standby There is no consumption on the I/Os of the device Figure 190 presents the power consumption estimated on the power supply. Figure 190. Power Consumption versus MCK Frequency in the Ultra Low Power Mode Current Consumption at 3.3V 100 35.2 35.3 35.7 36.4 37.7 40.5 46 10 0.5 1 2 4 Frequency (KHz) 8 16 32 450 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 Consumption (A) AT91SAM7S Preliminary Crystal Oscillators Characteristics RC Oscillator Characteristics Table 92. RC Oscillator Characteristics Symbol 1/(t CPRC) Parameter RC Oscillator Frequency Duty Cycle tST IOSC Startup Time Current Consumption VDDPLL = 1.65V After Startup Time Conditions VDDPLL = 1.65V Min 22 45 Typ 32 50 Max 42 55 75 1.9 Unit KHz % s A Main Oscillator Characteristics Table 93. Main Oscillator Characteristics Symbol 1/(t CPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2 ) Equivalent Load Capacitance Duty Cycle tST Startup Time VDDPLL = 1.2 to 2V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Active mode Standby mode Notes: 1. CS is the shunt capacitance 40 Conditions Min 3 Typ 16 25 12.5 50 60 14.5 1.4 1 550 1 Max 20 Unit MHz pF pF % ms IOSC Current Consumption A A XIN Clock Characteristics Table 94. XIN Clock Electrical Characteristics Symbol 1/(t CPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Note: Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pull-down Resistor (1) (1) Conditions Min Max 50.0 Units MHz ns 20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500 pF k 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register, see "PMC Clock Generator Main Oscillator Register" on page 171). 451 6070A-ATARM-28-Oct-04 PLL Characteristics Table 95. Phase Lock Loop Characteristics Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency Current Consumption Active mode Standby mode Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. Conditions 00 Field out of CKGR_PLL is: 10 150 1 220 32 4 1 MHz MHz mA A Min 80 Typ Max 160 Unit MHz 452 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary ADC Characteristics Table 96. Channel Conversion Time and ADC CLock Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate ADC Clock = 5 MHz ADC Clock = 5 MHz Return from Idle Mode 600 2 384 Conditions Min Typ Max 5 20 Units MHz s ns s kSPS Table 97. External Voltage Reference Input Conditions Parameter ADVREF Input Voltage Range ADVREF Average Current On 13 samples with ADC Clock = 5 MHz Min 2.6 12 Max VDDIN 250 Units V A Table 98. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 1 12 14 Typ Max VADVREF A pF Units Table 99. Transfer Characteristics Parameter Resolution Integral Non-linearity ADC Clock = 5 MHz Differential Non-linearity ADC Clock = 5 MHz Offset Error Gain Error 2 2 2 LSB LSB LSB 3 1 LSB LSB Conditions Min Typ 10 2 Max Units Bit LSB 453 6070A-ATARM-28-Oct-04 AT91SAM7S64 AC Characteristics Applicable Conditions and Derating Data These conditions and derating process apply to the following paragraphs: Clock Characteristics, Embedded Flash Characteristics and JTAG/ICE Timings. Conditions and Timings Computation All delays are given as typical values under the following conditions: * * * * * * VDDIO = 3.3V VDDCORE = 1.8V Ambient Temperature = 25C Load Capacitance = 0 pF The output level change detection is (0.5 x VDDIO). The input level is 0.8V for a low-level detection and is 2.0V for a high-level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account process variation and design. In order to obtain the timing for other conditions, the following equation should be used: * * * * * * T is the derating factor in temperature given in Figure 191 on page 455. VDDCORE is the derating factor for the Core Power Supply given in Figure 192 on page 455. tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. VDDIO is the derating factor for the IO Power Supply given in Figure 193 on page 456. CSIGNAL is the capacitance load on the considered output pin(1). CSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The user must take into account the package capacitance load contribution (CIN ) described in Table 87, "DC Characteristics," on page 444. The input delays are given as typical values. Note: 454 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 t = T x ( ( VDDCORE x t DATASHEET ) + ( VDDIO x where: ( C SIGNAL x CSIGNAL ) ) ) AT91SAM7S Preliminary Temperature Derating Factor Figure 191. Derating Curve for Different Operating Temperatures 1,1 1,05 Derating Factor 1 0,95 0,9 0,85 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Operating Temperature (C) VDDCORE Voltage Derating Factor Figure 192. Derating Curve for Different Core Supply Voltages 1,2 1,15 1,1 Derating Factor 1,05 1 0,95 0,9 0,85 0,8 1,65 1,7 1,75 1,8 Core Supply Voltage (V) 1,85 1,9 1,95 455 6070A-ATARM-28-Oct-04 VDDIO Voltage Derating Factor Figure 193. Derating Curve for Different IO Supply Voltages 1,15 1,1 Derating Factor 1,05 1 0,95 0,9 0,85 3 3,1 3,2 3,3 3,4 3,5 3,6 I/O Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. 456 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Clock Characteristics These parameters are given in the following conditions: * * VDDCORE = 1.8V Ambient Temperature = 25C The Temperature Derating Factor described in "Applicable Conditions and Derating Data" on page 454 and "VDDCORE Voltage Derating Factor" on page 455 are both applicable to these characteristics. Master Clock Characteristics Table 100. Master Clock Waveform Parameters Symbol 1/(t CPMCK) Parameter Master Clock Frequency Conditions Min Max 73 Units MHz 457 6070A-ATARM-28-Oct-04 Embedded Flash Characteristics Table 101. DC Flash Characteristics Symbol TPU ISB Parameter Power-up delay Standby current @85C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V Random Read @ 40MHz onto VDDCORE = 1.8V onto VDDFLASH = 3.3V ICC Active current Write onto VDDCORE = 1.8V onto VDDFLASH = 3.3V 500 8.0 A mA Conditions Min Max 30 0 30 5.0 1.0 Units S A mA The maximum operating frequency is given in Table 101 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 102 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 102. Embedded Flash Wait States FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Maximum Operating Frequency (MHz) 40 1/(tCPMCK) 1/(tCPMCK) 1/(tCPMCK) Table 103. AC Flash Characteristics Parameter Program Cycle Time per page without auto-erase Full Chip Erase 10 2 ms ms Conditions per page including auto-erase Min Max 4 Units ms 458 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary JTAG/ICE Timings ICE Interface Signals Table 104 shows timings relative to operating condition limits defined in the section "Conditions and Timings Computation" on page 454. Table 104. ICE Interface Timing Specification Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating Conditions Min 51 51 102 3 0 3 0.037 13 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF ICE6 Figure 194. ICE Interface Signals ICE2 TCK ICE0 ICE1 TMS/TDI ICE3 ICE4 TDO ICE5 ICE6 459 6070A-ATARM-28-Oct-04 JTAG Interface Signals The following table shows timings relative to operating condition limits defined in the section "Conditions and Timings Computation" on page 454. Table 105. JTAG Interface Timing specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time COUT = 0 pF COUT derating TCK to Device Outputs Valid COUT = 0 pF COUT derating CTDO = 0 pF CTDO derating 0 3 4 0.037 20 0.037 Conditions Min 6.5 5.5 12 2 3 2 0.037 15 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 460 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Figure 195. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8 Device Outputs JTAG9 JTAG10 461 6070A-ATARM-28-Oct-04 AT91SAM7S64 Mechanical Characteristics Thermal Considerations Thermal Data In Table 106, the device lifetime is estimated using the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 463.) Note that the user must be extremely cautious with this MTBF calculation. It should be noted that the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 106. MTBF Versus Junction Temperature Junction Temperature (TJ) (C) 100 125 150 175 Estimated Lifetime (MTBF) (Year) 17 9 5 3 Table 107 summarizes the thermal resistance data depending on the package. Table 107. Thermal Resistance Data Symbol JA JC Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package LQFP64 LQFP64 Typ 47.2 Unit C/W 12.2 462 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 4. 5. T J = T A + ( P D x JA ) T J = T A + ( P D x ( HEATSINK + JC ) ) where: * * * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 107 on page 462. JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 107 on page 462. HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 446. TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C. Package Drawings Figure 196. 64-lead LQFP Package Drawing 463 6070A-ATARM-28-Oct-04 Table 108. 64-lead LQFP Package Dimensions (in mm) Table 109. Device and 64-lead LQFP Package Maximum Weight 700 mg Table 110. 64-lead LQFP Package Characteristics Moisture Sensitivity Level 3 464 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S Preliminary Soldering Profile Table 111 gives the recommended soldering profile from J-STD-20. Table 111. Soldering Profile Convection or IR/Convection Average Ramp-up Rate (183C to Peak) Preheat Temperature 125C 25C Temperature Maintained Above 183C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature 3C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0C or 235 +5/-0C 6C/sec. 6 min. max 60 sec. 215 to 219C or 235 +5/-0C 10C/sec. VPR 10C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235C, not 220C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 112. Table 112. Recommended Package Reflow Conditions (1, 2, 3) Parameter Convection VPR IR/Convection Temperature 235 +5/-0C 235 +5/-0C 235 +5/-0C When certain small thin packages are used on boards without larger packages, these small packages may be classified at 220C instead of 235C. Notes: 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220C (unless 235C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. A maximum of three reflow passes is allowed per component. 465 6070A-ATARM-28-Oct-04 AT91SAM7S64 Ordering Information Table 113. Ordering Information Ordering Code AT91SAMS64-AI Package LQFP 64 Temperature Operating Range Industrial (-40C to 85C) 466 AT91SAM7S Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Table of Contents Features............................................................................................................... 1 Description .......................................................................................................... 2 Block Diagram..................................................................................................... 3 Signal Description .............................................................................................. 4 Package and Pinout............................................................................................ 7 64-lead LQFP Mechanical Overview................................................................ 7 Pinout ............................................................................................................... 7 Power Considerations........................................................................................ 8 Power Supplies ................................................................................................ 8 Power Consumption ......................................................................................... 8 Voltage Regulator ............................................................................................ 8 Typical Powering Schematics .......................................................................... 9 I/O Lines Considerations ................................................................................. 10 JTAG Port Pins .............................................................................................. 10 Test Pin .......................................................................................................... 10 Reset Pin........................................................................................................ 10 ERASE Pin ..................................................................................................... 10 PIO Controller A Lines ................................................................................... 10 I/O Line Drive Levels...................................................................................... 10 Processor and Architecture............................................................................. 11 ARM7TDMI Processor ................................................................................... 11 Debug and Test Features .............................................................................. 11 Memory Controller.......................................................................................... 11 Peripheral Data Controller.............................................................................. 12 Memory .............................................................................................................. 13 Memory Mapping ........................................................................................... 13 Embedded Flash ............................................................................................ 14 Fast Flash Programming Interface ................................................................. 15 System Controller............................................................................................. 16 System Controller Mapping ............................................................................ 17 Reset Controller ............................................................................................. 18 Clock Generator ............................................................................................. 19 Power Management Controller ...................................................................... 20 Advanced Interrupt Controller ........................................................................ 20 Debug Unit ..................................................................................................... 21 Periodic Interval Timer ................................................................................... 21 Watchdog Timer............................................................................................. 21 Real-time Timer.............................................................................................. 21 PIO Controller ................................................................................................ 21 Voltage Regulator Controller.......................................................................... 22 Peripherals ........................................................................................................ 23 Peripheral Mapping ........................................................................................ 23 Peripheral Multiplexing on PIO Lines ............................................................. 24 PIO Controller A Multiplexing ......................................................................... 25 Peripheral Identifiers ...................................................................................... 26 Serial Peripheral Interface.............................................................................. 26 i 6070A-ATARM-28-Oct-04 Two-wire Interface.......................................................................................... USART ........................................................................................................... Serial Synchronous Controller ....................................................................... Timer Counter ................................................................................................ PWM Controller .............................................................................................. USB Device Port ............................................................................................ Analog-to-digital Converter ............................................................................ 27 27 27 27 28 28 28 ARM7TDMI Processor Overview .................................................................. 31 Overview............................................................................................................ ARM7TDMI Processor ...................................................................................... Instruction Type.............................................................................................. Data Type....................................................................................................... ARM7TDMI Operating Mode.......................................................................... ARM7TDMI Registers .................................................................................... ARM Instruction Set Overview ....................................................................... Thumb Instruction Set Overview .................................................................... 31 32 32 32 32 32 34 35 AT91SAM7S64 Debug and Test Features ................................................... 37 Description ........................................................................................................ Block Diagram................................................................................................... Application Examples ...................................................................................... Debug Environment ....................................................................................... Test Environment ........................................................................................... Debug and Test Pin Description ..................................................................... Functional Description..................................................................................... Test Pin.............................................................................................................. Embedded In-circuit Emulator ........................................................................ Debug Unit ..................................................................................................... IEEE 1149.1 JTAG Boundary Scan ............................................................... ID Code Register............................................................................................ 37 37 38 38 39 39 40 40 40 40 40 44 Reset Controller (RSTC) ............................................................................... 45 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... NRST Manager .............................................................................................. Brownout Manager ......................................................................................... Reset States................................................................................................... Reset State Priorities ..................................................................................... Reset Controller Status Register.................................................................... Reset Controller (RSTC) User Interface.......................................................... Reset Controller Control Register .................................................................. Reset Controller Status Register.................................................................... Reset Controller Mode Register..................................................................... 45 45 46 46 47 48 53 53 55 56 57 58 ii AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Real-time Timer (RTT) ................................................................................... 59 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Real-time Timer (RTT) User Interface ............................................................. Real-time Timer Mode Register ..................................................................... Real-time Timer Alarm Register..................................................................... Real-time Timer Value Register ..................................................................... Real-time Timer Status Register .................................................................... 59 59 60 62 63 64 65 66 Periodic Interval Timer (PIT)......................................................................... 67 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Periodic Interval Timer (PIT) User Interface ................................................... Periodic Interval Timer Mode Register ........................................................... Periodic Interval Timer Status Register.......................................................... Periodic Interval Timer Value Register........................................................... Periodic Interval Timer Image Register .......................................................... 67 67 68 70 71 72 73 74 Watchdog Timer (WDT) ................................................................................. 75 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Watchdog Timer (WDT) User Interface ........................................................... Watchdog Timer Control Register .................................................................. Watchdog Timer Mode Register .................................................................... Watchdog Timer Status Register ................................................................... 75 75 76 78 79 80 81 Voltage Regulator Mode Controller (VREG)................................................ 83 Overview............................................................................................................ 83 Voltage Regulator Power Controller (VREG) User Interface ........................ 83 Voltage Regulator Mode Register .................................................................. 83 Memory Controller (MC)................................................................................ 85 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Bus Arbiter ..................................................................................................... Address Decoder ........................................................................................... Remap Command .......................................................................................... Abort Status ................................................................................................... Embedded Flash Controller ........................................................................... Misalignment Detector ................................................................................... 85 85 86 86 86 87 88 88 88 iii 6070A-ATARM-28-Oct-04 Memory Controller (MC) User Interface .......................................................... MC Remap Control Register .......................................................................... MC Abort Status Register .............................................................................. MC Abort Address Status Register ................................................................ 89 90 91 92 Embedded Flash Controller (EFC) ............................................................... 93 Overview............................................................................................................ 93 Functional Description..................................................................................... 93 Embedded Flash Organization....................................................................... 93 Read Operations ............................................................................................ 95 Write Operations ............................................................................................ 97 Flash Commands ........................................................................................... 97 Embedded Flash Controller (EFC) User Interface ....................................... 102 MC Flash Mode Register ............................................................................. 103 MC Flash Command Register ...................................................................... 104 MC Flash Status Register ............................................................................ 106 Fast Flash Programming Interface (FFPI) ................................................. 107 Overview.......................................................................................................... Parallel Fast Flash Programming.................................................................. Device Configuration.................................................................................... Signal Names............................................................................................... Entering Programming Mode ....................................................................... Read Handshaking....................................................................................... Device Operations........................................................................................ Serial Fast Flash Programming..................................................................... Device Configuration.................................................................................... Entering Serial Programming Mode ............................................................. Read/Write Handshake ................................................................................ Device Operations........................................................................................ 107 108 108 109 110 111 112 116 116 117 117 118 Peripheral Data Controller (PDC) ............................................................... 121 Overview.......................................................................................................... Block Diagram................................................................................................. Functional Description................................................................................... Configuration................................................................................................ Memory Pointers .......................................................................................... Transfer Counters ........................................................................................ Data Transfers ............................................................................................. Priority of PDC Transfer Requests ............................................................... Peripheral Data Controller (PDC) User Interface ......................................... PDC Receive Pointer Register..................................................................... PDC Receive Counter Register ................................................................... PDC Transmit Pointer Register .................................................................... PDC Transmit Counter Register .................................................................. 121 121 122 122 122 122 123 123 124 125 125 126 126 iv AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary PDC Receive Next Pointer Register ............................................................ PDC Receive Next Counter Register ........................................................... PDC Transmit Next Pointer Register ........................................................... PDC Transmit Next Counter Register .......................................................... PDC Transfer Control Register .................................................................... PDC Transfer Status Register...................................................................... 127 127 128 128 129 130 Advanced Interrupt Controller (AIC) .......................................................... 131 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ AIC Detailed Block Diagram .......................................................................... I/O Line Description........................................................................................ Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... Interrupt Source Control............................................................................... Interrupt Latencies ....................................................................................... Normal Interrupt ........................................................................................... Fast Interrupt................................................................................................ Protect Mode................................................................................................ Spurious Interrupt......................................................................................... General Interrupt Mask ................................................................................ Advanced Interrupt Controller (AIC) User Interface .................................... Base Address............................................................................................... AIC Source Mode Register .......................................................................... AIC Source Vector Register ......................................................................... AIC Interrupt Vector Register ....................................................................... AIC FIQ Vector Register ...................................................................................... AIC Interrupt Status Register ....................................................................... AIC Interrupt Pending Register .................................................................... AIC Interrupt Mask Register ......................................................................... AIC Core Interrupt Status Register .............................................................. AIC Interrupt Enable Command Register..................................................... AIC Interrupt Disable Command Register .................................................... AIC Interrupt Clear Command Register ....................................................... AIC Interrupt Set Command Register .......................................................... AIC End of Interrupt Command Register ..................................................... AIC Spurious Interrupt Vector Register ........................................................ AIC Debug Control Register......................................................................... AIC Fast Forcing Enable Register................................................................ AIC Fast Forcing Disable Register ............................................................... AIC Fast Forcing Status Register................................................................. 131 131 131 132 132 132 132 132 132 134 134 136 137 139 142 143 143 144 144 145 146 146 147 148 148 149 149 150 150 151 151 152 152 153 153 154 154 v 6070A-ATARM-28-Oct-04 Clock Generator........................................................................................... 155 Description ...................................................................................................... Slow Clock RC Oscillator ............................................................................. Main Oscillator ............................................................................................. Divider and PLL Block .................................................................................. 155 155 155 157 Power Management Controller (PMC) ....................................................... 158 Description ................................................................................................... Master Clock Controller................................................................................ Processor Clock Controller .......................................................................... USB Clock Controller ................................................................................... Peripheral Clock Controller .......................................................................... Programmable Clock Output Controller ....................................................... Programming Sequence .............................................................................. Clock Switching Details ................................................................................ Power Management Controller (PMC) User Interface ................................ 158 158 158 159 159 159 160 163 166 Debug Unit (DBGU) ..................................................................................... 179 Overview.......................................................................................................... Block Diagram................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Source ........................................................................................... UART Operations............................................................................................ Baud Rate Generator ................................................................................... Receiver ....................................................................................................... Transmitter ................................................................................................... Peripheral Data Controller............................................................................ Test Modes .................................................................................................. Debug Communication Channel Support..................................................... Chip Identifier ............................................................................................... ICE Access Prevention ................................................................................ Debug Unit User Interface ............................................................................. Debug Unit Control Register ........................................................................ Debug Unit Mode Register ........................................................................... Debug Unit Interrupt Enable Register .......................................................... Debug Unit Interrupt Disable Register ......................................................... Debug Unit Interrupt Mask Register ............................................................. Debug Unit Status Register.......................................................................... Debug Unit Receiver Holding Register ........................................................ Debug Unit Transmit Holding Register......................................................... Debug Unit Baud Rate Generator Register.................................................. Debug Unit Chip ID Register........................................................................ 179 180 181 181 181 181 181 181 182 184 185 185 186 187 187 188 189 190 191 192 193 194 196 197 197 198 vi AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Debug Unit Chip ID Extension Register ....................................................... 201 Debug Unit Force NTRST Register.............................................................. 201 Parallel Input/Output Controller (PIO) ....................................................... 203 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... Pin Multiplexing ............................................................................................ External Interrupt Lines ................................................................................ Power Management ..................................................................................... Interrupt Generation ..................................................................................... Functional Description................................................................................... Pull-up Resistor Control ............................................................................... I/O Line or Peripheral Function Selection .................................................... Peripheral A or B Selection .......................................................................... Output Control.............................................................................................. Synchronous Data Output............................................................................ Multi Drive Control (Open Drain) .................................................................. Output Line Timings ..................................................................................... Inputs ........................................................................................................... Input Glitch Filtering ..................................................................................... Input Change Interrupt ................................................................................. I/O Lines Programming Example .................................................................. Parallel Input/Output Controller (PIO) User Interface.................................. PIO Controller PIO Enable Register............................................................. PIO Controller PIO Disable Register............................................................ PIO Controller PIO Status Register.............................................................. PIO Controller Output Enable Register ........................................................ PIO Controller Output Disable Register ....................................................... PIO Controller Output Status Register ......................................................... PIO Controller Input Filter Enable Register .................................................. PIO Controller Input Filter Disable Register ................................................. PIO Controller Input Filter Status Register................................................... PIO Controller Set Output Data Register ..................................................... PIO Controller Clear Output Data Register .................................................. PIO Controller Output Data Status Register ................................................ PIO Controller Pin Data Status Register ...................................................... PIO Controller Interrupt Enable Register ..................................................... PIO Controller Interrupt Disable Register..................................................... PIO Controller Interrupt Mask Register ........................................................ PIO Controller Interrupt Status Register ...................................................... PIO Multi-driver Enable Register.................................................................. PIO Multi-driver Disable Register................................................................. PIO Multi-driver Status Register................................................................... PIO Pull Up Disable Register ....................................................................... 203 204 204 205 205 205 205 205 206 206 207 207 207 208 208 208 208 209 209 211 212 214 214 215 215 216 216 217 217 218 218 219 219 220 220 221 221 222 222 223 223 224 vii 6070A-ATARM-28-Oct-04 PIO Pull Up Enable Register........................................................................ PIO Pull Up Status Register ......................................................................... PIO Peripheral A Select Register................................................................. PIO Peripheral B Select Register................................................................. PIO Peripheral A B Status Register ............................................................. PIO Output Write Enable Register ............................................................... PIO Output Write Disable Register .............................................................. PIO Output Write Status Register ................................................................ 224 225 225 226 226 227 227 228 Serial Peripheral Interface (SPI) ................................................................. 229 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Signal Description ......................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Modes of Operation...................................................................................... Data Transfer ............................................................................................... Master Mode Operations.............................................................................. SPI Slave Mode ........................................................................................... Serial Peripheral Interface (SPI) User Interface .......................................... SPI Control Register .................................................................................... SPI Mode Register ....................................................................................... SPI Receive Data Register .......................................................................... SPI Transmit Data Register ......................................................................... SPI Status Register...................................................................................... SPI Interrupt Enable Register ...................................................................... SPI Interrupt Disable Register...................................................................... SPI Interrupt Mask Register ......................................................................... SPI Chip Select Register.............................................................................. 229 230 230 231 231 231 231 231 232 232 232 234 239 241 242 243 245 246 247 249 250 251 252 Two-wire Interface (TWI) ............................................................................. 255 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... I/O Lines Description.................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Transfer Format ........................................................................................... Modes of Operation...................................................................................... 255 255 255 256 256 256 256 257 257 257 viii AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Transmitting Data ......................................................................................... Read/Write Flowcharts................................................................................. Two-wire Interface (TWI) User Interface ...................................................... TWI Control Register.................................................................................... TWI Master Mode Register .......................................................................... TWI Internal Address Register ..................................................................... TWI Clock Waveform Generator Register.................................................... TWI Status Register ..................................................................................... TWI Interrupt Enable Register...................................................................... TWI Interrupt Disable Register..................................................................... TWI Interrupt Mask Register ........................................................................ TWI Receive Holding Register ..................................................................... TWI Transmit Holding Register .................................................................... 257 260 262 263 264 265 265 266 267 268 269 270 270 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 271 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ I/O Lines Description ..................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Baud Rate Generator ................................................................................... Receiver and Transmitter Control ................................................................ Synchronous and Asynchronous Modes...................................................... ISO7816 Mode ............................................................................................. IrDA Mode .................................................................................................... RS485 Mode ................................................................................................ Modem Mode ............................................................................................... Test Modes .................................................................................................. USART User Interface ................................................................................... USART Control Register .............................................................................. USART Mode Register................................................................................. USART Interrupt Enable Register ................................................................ USART Interrupt Disable Register ............................................................... USART Interrupt Mask Register................................................................... USART Channel Status Register ................................................................. USART Receive Holding Register ............................................................... USART Transmit Holding Register .............................................................. USART Baud Rate Generator Register ....................................................... USART Receiver Time-out Register ............................................................ USART Transmitter Timeguard Register ..................................................... USART FI DI RATIO Register ...................................................................... USART Number of Errors Register .............................................................. 271 272 273 273 274 274 274 274 275 275 279 279 289 291 294 295 296 298 299 301 304 305 306 307 309 309 310 311 312 313 314 ix 6070A-ATARM-28-Oct-04 USART IrDA FILTER Register ..................................................................... 314 Synchronous Serial Controller (SSC)........................................................ 315 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Clock Management ...................................................................................... Clock Divider ................................................................................................ Transmitter Operations ................................................................................ Receiver Operations .................................................................................... Start.............................................................................................................. Frame Sync.................................................................................................. Data Format ................................................................................................. Loop Mode ................................................................................................... Interrupt........................................................................................................ SSC Application Examples ............................................................................ Synchronous Serial Controller (SSC) User Interface ................................. SSC Control Register................................................................................... SSC Clock Mode Register ........................................................................... SSC Receive Clock Mode Register ............................................................. SSC Receive Frame Mode Register ............................................................ SSC Transmit Clock Mode Register ............................................................ SSC Transmit Frame Mode Register ........................................................... SSC Receive Holding Register .................................................................... SSC Transmit Holding Register ................................................................... SSC Receive Synchronization Holding Register.......................................... SSC Transmit Synchronization Holding Register......................................... SSC Status Register .................................................................................... SSC Interrupt Enable Register..................................................................... SSC Interrupt Disable Register .................................................................... SSC Interrupt Mask Register ....................................................................... 315 315 316 317 317 317 317 317 317 318 319 321 322 322 324 324 326 326 328 330 331 331 332 334 336 338 340 340 341 341 342 344 345 346 Timer/Counter (TC)...................................................................................... 347 Overview.......................................................................................................... Block Diagram................................................................................................. Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... 347 347 348 348 348 348 x AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Interrupt........................................................................................................ Functional Description................................................................................... TC Description ............................................................................................. Capture Operating Mode.............................................................................. Waveform Operating Mode .......................................................................... Timer/Counter (TC) User Interface ................................................................ Global Register Mapping ............................................................................. Channel Memory Mapping ........................................................................... TC Block Control Register............................................................................ TC Block Mode Register .............................................................................. TC Channel Control Register ....................................................................... TC Channel Mode Register: Capture Mode ................................................. TC Channel Mode Register: Waveform Mode ............................................. TC Counter Value Register .......................................................................... TC Register A............................................................................................... TC Register B............................................................................................... TC Register C .............................................................................................. TC Status Register ....................................................................................... TC Interrupt Enable Register ....................................................................... TC Interrupt Disable Register....................................................................... TC Interrupt Mask Register .......................................................................... 348 348 348 351 353 360 360 360 361 361 362 363 365 368 368 369 369 370 372 373 374 Pulse Width Modulation Controller (PWM) ............................................... 375 Overview.......................................................................................................... Block Diagram................................................................................................. I/O Lines Description...................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... PWM Clock Generator ................................................................................. PWM Channel .............................................................................................. PWM Controller Operations ......................................................................... PWM User Interface ........................................................................................ PWM Register Mapping ............................................................................... PWM Mode Register .................................................................................... PWM Enable Register .................................................................................. PWM Disable Register ................................................................................. PWM Status Register................................................................................... PWM Interrupt Enable Register ................................................................... PWM Interrupt Disable Register................................................................... PWM Interrupt Mask Register ...................................................................... PWM Interrupt Status Register .................................................................... PWM Channel Mode Register...................................................................... PWM Channel Duty Cycle Register ............................................................. 375 375 376 376 376 376 376 377 377 378 382 384 384 385 386 386 387 388 388 389 389 390 391 xi 6070A-ATARM-28-Oct-04 PWM PWM PWM PWM Channel Period Register .................................................................... Channel Counter Register .................................................................. Channel Update Register ................................................................... Version Register................................................................................. 392 393 393 394 USB Device Port (UDP) ............................................................................... 395 Overview.......................................................................................................... Block Diagram................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Typical Connection......................................................................................... Functional Description................................................................................... USB V2.0 Full-speed Introduction ................................................................ Handling Transactions with USB V2.0 Device Peripheral............................ Controlling Device States............................................................................. USB Device Port (UDP) User Interface ......................................................... USB Frame Number Register ...................................................................... USB Global State Register........................................................................... USB Function Address Register .................................................................. USB Interrupt Enable Register..................................................................... USB Interrupt Disable Register .................................................................... USB Interrupt Mask Register ....................................................................... USB Interrupt Status Register ...................................................................... USB Interrupt Clear Register ....................................................................... USB Reset Endpoint Register ...................................................................... USB Endpoint Control and Status Register ................................................. USB FIFO Data Register.............................................................................. USB Transceiver Control Register ............................................................... 395 395 396 396 396 396 397 398 398 399 409 411 412 413 414 415 416 417 418 420 421 422 425 426 Analog-to-digital Converter (ADC) ............................................................. 427 Overview.......................................................................................................... Block Diagram................................................................................................. Signal Description .......................................................................................... Product Dependencies................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Analog Inputs ............................................................................................... I/O Lines....................................................................................................... Timer Triggers .............................................................................................. Conversion Performances............................................................................ Functional Description................................................................................... Analog-to-digital Conversion ........................................................................ Conversion Reference ................................................................................. 427 427 428 428 428 428 428 428 428 428 429 429 429 xii AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Conversion Resolution ................................................................................. Conversion Results ...................................................................................... Conversion Triggers ..................................................................................... Sleep Mode and Conversion Sequencer ..................................................... ADC Timings ................................................................................................ Analog-to-digital Converter (ADC) User Interface ....................................... ADC Control Register................................................................................... ADC Mode Register ..................................................................................... ADC Channel Enable Register..................................................................... ADC Channel Disable Register .................................................................... ADC Channel Status Register...................................................................... ADC Status Register .................................................................................... ADC Last Converted Data Register ............................................................. ADC Interrupt Enable Register..................................................................... ADC Interrupt Disable Register .................................................................... 429 429 431 432 432 433 434 435 437 437 438 439 440 441 442 AT91SAM7S64 Electrical Characteristics ................................................. 443 Absolute Maximum Ratings........................................................................... DC Characteristics.......................................................................................... Power Consumption....................................................................................... Power Consumption Versus Modes ............................................................. Peripheral Power Consumption in Active Mode ........................................... Power Consumption versus Master Clock Frequency in Active Mode......... Power Consumption versus Master Clock Frequency in Ultra Low-power Mode ................................................................................. Crystal Oscillators Characteristics ............................................................... RC Oscillator Characteristics ....................................................................... Main Oscillator Characteristics..................................................................... XIN Clock Characteristics ............................................................................ PLL Characteristics ........................................................................................ ADC Characteristics ...................................................................................... 443 444 446 446 448 449 450 451 451 451 451 452 453 AT91SAM7S64 AC Characteristics ............................................................ 454 Applicable Conditions and Derating Data .................................................... Conditions and Timings Computation .......................................................... Temperature Derating Factor ....................................................................... VDDCORE Voltage Derating Factor ............................................................ VDDIO Voltage Derating Factor................................................................... Clock Characteristics ..................................................................................... Master Clock Characteristics ....................................................................... Embedded Flash Characteristics ................................................................. JTAG/ICE Timings .......................................................................................... ICE Interface Signals ................................................................................... JTAG Interface Signals ................................................................................ 454 454 455 455 456 457 457 458 459 459 460 xiii 6070A-ATARM-28-Oct-04 AT91SAM7S64 Mechanical Characteristics .............................................. 462 Thermal Considerations................................................................................. Thermal Data ............................................................................................... Junction Temperature .................................................................................. Package Drawings .......................................................................................... Soldering Profile ............................................................................................. AT91SAM7S64 Ordering Information............................................................ 462 462 463 463 465 466 Table of Contents i Revision History ............................................................................................... xv xiv AT91SAM7S64 Preliminary 6070A-ATARM-28-Oct-04 AT91SAM7S64 Preliminary Revision History Doc. Rev 6070A Comments * Date: 28-Oct-04 xv 6070A-ATARM-28-Oct-04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) Atmel Corporation 2004. All rights reserved. ATMEL (R) and combinations thereof and DataFlash(R) are the registered trademarks and and Everywhere You Are SM is the trademark of Atmel Corporation or its subsidiaries. ARM (R), ARM Powered (R), ARM7TDMI(R) and Thumb (R) are the registered trademarks and ARM9TDMITM, ARM920T TM and AMBA TM are the trademarks of ARM Ltd.; CompactFlash(R) is a registered trademark of the CompactFlash Association; SmartMedia TM is a trademark of the Solid State Floppy Disk Card Forum. Other terms and product names may be the trademarks of others. Printed on recycled paper. 6070A-ATARM-28-Oct-04 |
Price & Availability of AT91SAMS64-AI
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |